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authorFelix Held <felix-coreboot@felixheld.de>2021-06-15 20:09:40 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-06-16 19:16:44 +0000
commitaa7eb08dc869982b20fda48cabe8066ede0e92f0 (patch)
treeffa1ac31b3bed95851c5cb24a819bd7c142edec0 /src/southbridge/intel
parent97fc054979d709bd84861e046b451cf2abc97fbc (diff)
mb/google/zork: enable UART0 in devicetree
This a mainly a preparation for adding the MMIO UART devices to the chipset devicetree. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I533e4a909fdeb1614dbc5df015440b9df5d83233 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
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