diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-14 13:53:44 +0200 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-05-23 08:25:00 +0000 |
| commit | 6c42d14d45974fa5a1b08bbd3c48d8fa7945c4ee (patch) | |
| tree | be6c1da0409265aed167cb3290db5d574f85f7ac /src/southbridge/intel | |
| parent | 8a2c36467c259c965d9b7fbd24352deadf6a0a07 (diff) | |
nb/intel/haswell: Allow using Broadwell MRC.bin
This is needed to support 9-series PCH-H (e.g. Z97) and Broadwell
non-ULT CPUs (for which more magic is required).
Tested on Asrock Z97 Extreme6: Boots, but ME has to be disabled so that
the system remains on after 30 seconds. Apparently, something Broadwell
MRC.bin does results in the ME being unhappy, as there is no such issue
when not using MRC.bin at all (native RAM init). S3 resume is working.
Change-Id: I7b33660099fa75c5ad46aeeda17b1215729f96c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/bootblock.c | 15 |
3 files changed, 20 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index af346ab4c8..08042984be 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -45,6 +45,7 @@ config INTEL_LYNXPOINT_LP config EHCI_BAR hex + default 0xd8000000 if USE_BROADWELL_MRC default 0xe8000000 config SERIRQ_CONTINUOUS_MODE diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index bba89f4699..5088d8bb2d 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -34,10 +34,14 @@ smm-y += pmutil.c usb_ehci.c usb_xhci.c bootblock-y += early_pch.c romstage-y += early_usb.c early_me.c me_status.c early_pch.c romstage-y += pmutil.c +romstage-y += iobp.c romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c subdirs-$(CONFIG_USE_NATIVE_RAMINIT) += hsio +romstage-$(CONFIG_USE_BROADWELL_MRC) += early_pch_native.c early_usb_native.c iobp.c thermal.c +subdirs-$(CONFIG_USE_BROADWELL_MRC) += hsio + ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) romstage-y += lp_gpio.c ramstage-y += lp_gpio.c diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 495871c6d2..5bdebef418 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -52,6 +52,21 @@ void bootblock_early_southbridge_init(void) pch_enable_lpc(); mainboard_config_superio(); + /* Broadwell MRC.bin uses HPET, but does not enable it beforehand */ + if (CONFIG(USE_BROADWELL_MRC)) { + /* Set HPET address and enable it */ + RCBA32_AND_OR(HPTC, ~3, 1 << 7); + + /* + * Reading the register back guarantees that the write is + * done before we use the configured base address below. + */ + (void)RCBA32(HPTC); + + /* Enable HPET to start counter */ + setbits32((void *)0xfed00000 + 0x10, 1 << 0); + } + if (CONFIG(SERIALIO_UART_CONSOLE)) uart_bootblock_init(); } |