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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2019-03-04 15:14:29 +0100 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2019-03-16 09:01:50 +0000 |
| commit | 5926ae24a6fa4ebf83f24281c3df88b61076b838 (patch) | |
| tree | bb64e20821959f34603fd5bd72502d6da4dd18dd /src/southbridge/intel | |
| parent | 0e3f7d47804d39912faec5a56bc9cddf91ea354b (diff) | |
drivers/intel/fsp1_0: Deduplicate code
Move ChipsetFspReturnPoint() to drivers/intel/fsp1_0.
Allows to have a common entry after FSP-M.
Change-Id: I064ae67041c521ee92877cff30c814fce7b08e1f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/fsp_rangeley/romstage.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/southbridge/intel/fsp_rangeley/romstage.h b/src/southbridge/intel/fsp_rangeley/romstage.h index 261357746f..5827b0fe9b 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.h +++ b/src/southbridge/intel/fsp_rangeley/romstage.h @@ -29,6 +29,4 @@ void early_mainboard_romstage_entry(void); void late_mainboard_romstage_entry(void); void get_func_disables(uint32_t *mask); -void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); - #endif /* _RANGELEY_ROMSTAGE_H_ */ |