summaryrefslogtreecommitdiff
path: root/src/southbridge/intel
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2019-12-27 14:30:51 -0700
committerAaron Durbin <adurbin@chromium.org>2020-01-03 23:06:50 +0000
commit4ed8e9ce9dcd8c91acc8d8e45aca6486d3b9b879 (patch)
tree3d28c0897bb678f7b165db1b18ba0ac307089072 /src/southbridge/intel
parent8b1cdd55a9328dc58430fb6efcea8993d864437f (diff)
spi-generic: remove SPI_FLASH_SECTOR_ERASE_TIMEOUT_MS
There was one user of SPI_FLASH_SECTOR_ERASE_TIMEOUT_MS, southbridge/intel/common/spi.c. Remove the define and encode the 1 second timeout that it was wanting at the single use site. Change-Id: If33a1a04bc4d3441e90bf0ca305ddf71c4f8bb88 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/common/spi.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 63206d0a83..924fdcc810 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -31,6 +31,7 @@
#include <device/pci.h>
#include <spi_flash.h>
#include <spi-generic.h>
+#include <timer.h>
#include "spi.h"
@@ -739,7 +740,7 @@ static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset,
u32 start, end, erase_size;
int ret;
uint16_t hsfc;
- unsigned int timeout = 1000 * SPI_FLASH_SECTOR_ERASE_TIMEOUT_MS;
+ unsigned int timeout = 1000 * USECS_PER_MSEC; /* 1 second timeout */
erase_size = flash->sector_size;
if (offset % erase_size || len % erase_size) {