sb/intel/bd82x6x: Turn ME PCI register structs into unions

This allows dropping the `pci_read_dword_ptr` and `pci_write_dword_ptr`
wrappers.

Change-Id: I7a6916e535fbba9f05451d5302261418f950be83
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49993
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 105 insertions, 121 deletions

diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
index 51c19d1cec..a47991cdf3 100644
--- a/src/southbridge/intel/bd82x6x/early_me.c
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -24,24 +24,18 @@ static const char *me_ack_values[] = {
 	[ME_HFS_ACK_CONTINUE]	= "Continue to boot"
 };
 
-static inline void pci_read_dword_ptr(void *ptr, int offset)
-{
-	u32 dword = pci_read_config32(PCH_ME_DEV, offset);
-	memcpy(ptr, &dword, sizeof(dword));
-}
-
 void intel_early_me_status(void)
 {
-	struct me_hfs hfs;
-	struct me_gmes gmes;
+	union me_hfs hfs;
+	union me_gmes gmes;
 	u32 id = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID);
 
 	if ((id == 0xffffffff) || (id == 0x00000000) ||
 	    (id == 0x0000ffff) || (id == 0xffff0000)) {
 		printk(BIOS_DEBUG, "Missing Intel ME PCI device.\n");
 	} else {
-		pci_read_dword_ptr(&hfs, PCI_ME_HFS);
-		pci_read_dword_ptr(&gmes, PCI_ME_GMES);
+		hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
+		gmes.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_GMES);
 
 		intel_me_status(&hfs, &gmes);
 	}
@@ -50,14 +44,14 @@ void intel_early_me_status(void)
 int intel_early_me_init(void)
 {
 	int count;
-	struct me_uma uma;
-	struct me_hfs hfs;
+	union me_uma uma;
+	union me_hfs hfs;
 
 	printk(BIOS_INFO, "Intel ME early init\n");
 
 	/* Wait for ME UMA SIZE VALID bit to be set */
 	for (count = ME_RETRY; count > 0; --count) {
-		pci_read_dword_ptr(&uma, PCI_ME_UMA);
+		uma.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA);
 		if (uma.valid)
 			break;
 		udelay(ME_DELAY);
@@ -68,7 +62,7 @@ int intel_early_me_init(void)
 	}
 
 	/* Check for valid firmware */
-	pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+	hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
 	if (hfs.fpt_bad) {
 		printk(BIOS_WARNING, "WARNING: ME has bad firmware\n");
 		return -1;
@@ -80,9 +74,9 @@ int intel_early_me_init(void)
 
 int intel_early_me_uma_size(void)
 {
-	struct me_uma uma;
+	union me_uma uma;
 
-	pci_read_dword_ptr(&uma, PCI_ME_UMA);
+	uma.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA);
 	if (uma.valid) {
 		printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size);
 		return uma.size;
@@ -98,7 +92,7 @@ int intel_early_me_init_done(u8 status)
 	u32 mebase_l, mebase_h;
 	u32 millisec;
 	u32 hfs, me_fws2;
-	struct me_did did = {
+	union me_did did = {
 		.init_done = ME_INIT_DONE,
 		.status = status
 	};
diff --git a/src/southbridge/intel/bd82x6x/early_me_mrc.c b/src/southbridge/intel/bd82x6x/early_me_mrc.c
index 180e466bd4..9d46897fdf 100644
--- a/src/southbridge/intel/bd82x6x/early_me_mrc.c
+++ b/src/southbridge/intel/bd82x6x/early_me_mrc.c
@@ -22,31 +22,18 @@ static const char *me_ack_values[] = {
 	[ME_HFS_ACK_CONTINUE]	= "Continue to boot"
 };
 
-static inline void pci_read_dword_ptr(void *ptr, int offset)
-{
-	u32 dword = pci_read_config32(PCH_ME_DEV, offset);
-	memcpy(ptr, &dword, sizeof(dword));
-}
-
-static inline void pci_write_dword_ptr(void *ptr, int offset)
-{
-	u32 dword = 0;
-	memcpy(&dword, ptr, sizeof(dword));
-	pci_write_config32(PCH_ME_DEV, offset, dword);
-}
-
 void intel_early_me_status(void)
 {
-	struct me_hfs hfs;
-	struct me_gmes gmes;
+	union me_hfs hfs;
+	union me_gmes gmes;
 	u32 id = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID);
 
 	if ((id == 0xffffffff) || (id == 0x00000000) ||
 	    (id == 0x0000ffff) || (id == 0xffff0000)) {
 		printk(BIOS_DEBUG, "Missing Intel ME PCI device.\n");
 	} else {
-		pci_read_dword_ptr(&hfs, PCI_ME_HFS);
-		pci_read_dword_ptr(&gmes, PCI_ME_GMES);
+		hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
+		gmes.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_GMES);
 
 		intel_me_status(&hfs, &gmes);
 	}
@@ -55,14 +42,14 @@ void intel_early_me_status(void)
 int intel_early_me_init(void)
 {
 	int count;
-	struct me_uma uma;
-	struct me_hfs hfs;
+	union me_uma uma;
+	union me_hfs hfs;
 
 	printk(BIOS_INFO, "Intel ME early init\n");
 
 	/* Wait for ME UMA SIZE VALID bit to be set */
 	for (count = ME_RETRY; count > 0; --count) {
-		pci_read_dword_ptr(&uma, PCI_ME_UMA);
+		uma.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA);
 		if (uma.valid)
 			break;
 		udelay(ME_DELAY);
@@ -73,7 +60,7 @@ int intel_early_me_init(void)
 	}
 
 	/* Check for valid firmware */
-	pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+	hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
 	if (hfs.fpt_bad) {
 		printk(BIOS_WARNING, "WARNING: ME has bad firmware\n");
 		return -1;
@@ -85,9 +72,9 @@ int intel_early_me_init(void)
 
 int intel_early_me_uma_size(void)
 {
-	struct me_uma uma;
+	union me_uma uma;
 
-	pci_read_dword_ptr(&uma, PCI_ME_UMA);
+	uma.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA);
 	if (uma.valid) {
 		printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size);
 		return uma.size;
@@ -102,8 +89,8 @@ int intel_early_me_init_done(u8 status)
 	u8 reset;
 	int count;
 	u32 mebase_l, mebase_h;
-	struct me_hfs hfs;
-	struct me_did did = {
+	union me_hfs hfs;
+	union me_did did = {
 		.init_done = ME_INIT_DONE,
 		.status = status
 	};
@@ -117,11 +104,11 @@ int intel_early_me_init_done(u8 status)
 	printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, "
 	       "UMA base: 0x%04x\n", status, did.uma_base);
 
-	pci_write_dword_ptr(&did, PCI_ME_H_GS);
+	pci_write_config32(PCH_ME_DEV, PCI_ME_H_GS, did.raw);
 
 	/* Must wait for ME acknowledgement */
 	for (count = ME_RETRY; count > 0; --count) {
-		pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+		hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
 		if (hfs.bios_msg_ack)
 			break;
 		udelay(ME_DELAY);
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index cb263622cc..cda2540d82 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -31,15 +31,15 @@
 static me_bios_path intel_me_path(struct device *dev)
 {
 	me_bios_path path = ME_DISABLE_BIOS_PATH;
-	struct me_hfs hfs;
-	struct me_gmes gmes;
+	union me_hfs hfs;
+	union me_gmes gmes;
 
 	/* S3 wake skips all MKHI messages */
 	if (acpi_is_wakeup_s3())
 		return ME_S3WAKE_BIOS_PATH;
 
-	pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
-	pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES);
+	hfs.raw = pci_read_config32(dev, PCI_ME_HFS);
+	gmes.raw = pci_read_config32(dev, PCI_ME_GMES);
 
 	/* Check and dump status */
 	intel_me_status(&hfs, &gmes);
@@ -180,7 +180,7 @@ static void intel_me_init(struct device *dev)
 	me_bios_path path = intel_me_path(dev);
 	u8 me_state = 0, me_state_prev = 0;
 	bool need_reset = false;
-	struct me_hfs hfs;
+	union me_hfs hfs;
 
 	/* Do initial setup and determine the BIOS path */
 	printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_get_bios_path_string(path));
@@ -236,7 +236,7 @@ static void intel_me_init(struct device *dev)
 
 	case ME_DISABLE_BIOS_PATH:
 		/* Bring ME out of Soft Temporary Disable mode, if needed */
-		pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
+		hfs.raw = pci_read_config32(dev, PCI_ME_HFS);
 		if (hfs.operation_mode == ME_HFS_MODE_DIS
 				&& me_state == CMOS_ME_STATE_NORMAL
 				&& (CMOS_ME_STATE(me_state_prev) == CMOS_ME_STATE_DISABLED
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h
index 7e1a3bc19c..0cb64964cf 100644
--- a/src/southbridge/intel/bd82x6x/me.h
+++ b/src/southbridge/intel/bd82x6x/me.h
@@ -47,30 +47,36 @@
 #define  ME_HFS_ACK_GBL_RESET	6
 #define  ME_HFS_ACK_CONTINUE	7
 
-struct me_hfs {
-	u32 working_state: 4;
-	u32 mfg_mode: 1;
-	u32 fpt_bad: 1;
-	u32 operation_state: 3;
-	u32 fw_init_complete: 1;
-	u32 ft_bup_ld_flr: 1;
-	u32 update_in_progress: 1;
-	u32 error_code: 4;
-	u32 operation_mode: 4;
-	u32 reserved: 4;
-	u32 boot_options_present: 1;
-	u32 ack_data: 3;
-	u32 bios_msg_ack: 4;
+union me_hfs {
+	struct {
+		u32 working_state: 4;
+		u32 mfg_mode: 1;
+		u32 fpt_bad: 1;
+		u32 operation_state: 3;
+		u32 fw_init_complete: 1;
+		u32 ft_bup_ld_flr: 1;
+		u32 update_in_progress: 1;
+		u32 error_code: 4;
+		u32 operation_mode: 4;
+		u32 reserved: 4;
+		u32 boot_options_present: 1;
+		u32 ack_data: 3;
+		u32 bios_msg_ack: 4;
+	};
+	u32 raw;
 } __packed;
 
 #define PCI_ME_UMA		0x44
 
-struct me_uma {
-	u32 size: 6;
-	u32 reserved_1: 10;
-	u32 valid: 1;
-	u32 reserved_0: 14;
-	u32 set_to_one: 1;
+union me_uma {
+	struct {
+		u32 size: 6;
+		u32 reserved_1: 10;
+		u32 valid: 1;
+		u32 reserved_0: 14;
+		u32 set_to_one: 1;
+	};
+	u32 raw;
 } __packed;
 
 #define PCI_ME_H_GS		0x4c
@@ -79,11 +85,14 @@ struct me_uma {
 #define  ME_INIT_STATUS_NOMEM	1
 #define  ME_INIT_STATUS_ERROR	2
 
-struct me_did {
-	u32 uma_base: 16;
-	u32 reserved: 8;
-	u32 status: 4;
-	u32 init_done: 4;
+union me_did {
+	struct {
+		u32 uma_base: 16;
+		u32 reserved: 8;
+		u32 status: 4;
+		u32 init_done: 4;
+	};
+	u32 raw;
 } __packed;
 
 #define PCI_ME_GMES		0x48
@@ -95,21 +104,24 @@ struct me_did {
 #define  ME_GMES_PHASE_UNKNOWN	5
 #define  ME_GMES_PHASE_HOST	6
 
-struct me_gmes {
-	u32 bist_in_prog : 1;
-	u32 icc_prog_sts : 2;
-	u32 invoke_mebx : 1;
-	u32 cpu_replaced_sts : 1;
-	u32 mbp_rdy : 1;
-	u32 mfs_failure : 1;
-	u32 warm_rst_req_for_df : 1;
-	u32 cpu_replaced_valid : 1;
-	u32 reserved_1 : 2;
-	u32 fw_upd_ipu : 1;
-	u32 reserved_2 : 4;
-	u32 current_state: 8;
-	u32 current_pmevent: 4;
-	u32 progress_code: 4;
+union me_gmes {
+	struct {
+		u32 bist_in_prog : 1;
+		u32 icc_prog_sts : 2;
+		u32 invoke_mebx : 1;
+		u32 cpu_replaced_sts : 1;
+		u32 mbp_rdy : 1;
+		u32 mfs_failure : 1;
+		u32 warm_rst_req_for_df : 1;
+		u32 cpu_replaced_valid : 1;
+		u32 reserved_1 : 2;
+		u32 fw_upd_ipu : 1;
+		u32 reserved_2 : 4;
+		u32 current_state: 8;
+		u32 current_pmevent: 4;
+		u32 progress_code: 4;
+	};
+	u32 raw;
 } __packed;
 
 #define PCI_ME_HERES		0xbc
@@ -117,11 +129,14 @@ struct me_gmes {
 #define  PCI_ME_EXT_SHA256	0x02
 #define PCI_ME_HER(x)		(0xc0+(4*(x)))
 
-struct me_heres {
-	u32 extend_reg_algorithm: 4;
-	u32 reserved: 26;
-	u32 extend_feature_present: 1;
-	u32 extend_reg_valid: 1;
+union me_heres {
+	struct {
+		u32 extend_reg_algorithm: 4;
+		u32 reserved: 26;
+		u32 extend_feature_present: 1;
+		u32 extend_reg_valid: 1;
+	};
+	u32 raw;
 } __packed;
 
 /*
@@ -243,7 +258,6 @@ void mei_read_dword_ptr(void *ptr, int offset);
 void mei_write_dword_ptr(void *ptr, int offset);
 
 #ifndef __SIMPLE_DEVICE__
-void pci_read_dword_ptr(struct device *dev, void *ptr, int offset);
 bool enter_soft_temp_disable(void);
 void enter_soft_temp_disable_wait(void);
 void exit_soft_temp_disable(struct device *dev);
@@ -268,7 +282,7 @@ int intel_me_extend_valid(struct device *dev);
 void intel_me_hide(struct device *dev);
 
 /* Defined in me_status.c for both romstage and ramstage */
-void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
+void intel_me_status(union me_hfs *hfs, union me_gmes *gmes);
 
 void intel_early_me_status(void);
 int intel_early_me_init(void);
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index a0516b8e9b..abca881398 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -49,15 +49,15 @@ static void me_print_fw_version(mbp_fw_version_name *vers_name)
 static me_bios_path intel_me_path(struct device *dev)
 {
 	me_bios_path path = ME_DISABLE_BIOS_PATH;
-	struct me_hfs hfs;
-	struct me_gmes gmes;
+	union me_hfs hfs;
+	union me_gmes gmes;
 
 	/* S3 wake skips all MKHI messages */
 	if (acpi_is_wakeup_s3())
 		return ME_S3WAKE_BIOS_PATH;
 
-	pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
-	pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES);
+	hfs.raw = pci_read_config32(dev, PCI_ME_HFS);
+	gmes.raw = pci_read_config32(dev, PCI_ME_GMES);
 
 	/* Check and dump status */
 	intel_me_status(&hfs, &gmes);
@@ -178,7 +178,7 @@ static void intel_me_init(struct device *dev)
 	me_bios_payload mbp_data;
 	u8 me_state = 0, me_state_prev = 0;
 	bool need_reset = false;
-	struct me_hfs hfs;
+	union me_hfs hfs;
 
 	/* Do initial setup and determine the BIOS path */
 	printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_get_bios_path_string(path));
@@ -235,7 +235,7 @@ static void intel_me_init(struct device *dev)
 
 	case ME_DISABLE_BIOS_PATH:
 		/* Bring ME out of Soft Temporary Disable mode, if needed */
-		pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
+		hfs.raw = pci_read_config32(dev, PCI_ME_HFS);
 		if (hfs.operation_mode == ME_HFS_MODE_DIS
 				&& me_state == CMOS_ME_STATE_NORMAL
 				&& (CMOS_ME_STATE(me_state_prev) == CMOS_ME_STATE_DISABLED
diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c
index e229956607..1c6899d901 100644
--- a/src/southbridge/intel/bd82x6x/me_common.c
+++ b/src/southbridge/intel/bd82x6x/me_common.c
@@ -88,15 +88,6 @@ void mei_write_dword_ptr(void *ptr, int offset)
 	mei_dump(ptr, dword, offset, "WRITE");
 }
 
-#ifndef __SIMPLE_DEVICE__
-void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
-{
-	u32 dword = pci_read_config32(dev, offset);
-	memcpy(ptr, &dword, sizeof(dword));
-	mei_dump(ptr, dword, offset, "PCI READ");
-}
-#endif
-
 void read_host_csr(struct mei_csr *csr)
 {
 	mei_read_dword_ptr(csr, MEI_H_CSR);
@@ -368,11 +359,11 @@ int intel_mei_setup(struct device *dev)
 /* Read the Extend register hash of ME firmware */
 int intel_me_extend_valid(struct device *dev)
 {
-	struct me_heres status;
+	union me_heres status;
 	u32 extend[8] = {0};
 	int i, count = 0;
 
-	pci_read_dword_ptr(dev, &status, PCI_ME_HERES);
+	status.raw = pci_read_config32(dev, PCI_ME_HERES);
 	if (!status.extend_feature_present) {
 		printk(BIOS_ERR, "ME: Extend Feature not present\n");
 		return -1;
@@ -469,7 +460,7 @@ void exit_soft_temp_disable(struct device *dev)
 
 void exit_soft_temp_disable_wait(struct device *dev)
 {
-	struct me_hfs hfs;
+	union me_hfs hfs;
 	struct stopwatch sw;
 
 	stopwatch_init_msecs_expire(&sw, ME_ENABLE_TIMEOUT);
@@ -480,7 +471,7 @@ void exit_soft_temp_disable_wait(struct device *dev)
 	 */
 	do {
 		mdelay(50);
-		pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
+		hfs.raw = pci_read_config32(dev, PCI_ME_HFS);
 		if (hfs.fw_init_complete)
 			break;
 	} while (!stopwatch_expired(&sw));
diff --git a/src/southbridge/intel/bd82x6x/me_smm.c b/src/southbridge/intel/bd82x6x/me_smm.c
index 11f55c2cde..e1eb9001df 100644
--- a/src/southbridge/intel/bd82x6x/me_smm.c
+++ b/src/southbridge/intel/bd82x6x/me_smm.c
@@ -64,8 +64,7 @@ static int me7_mkhi_end_of_post(void)
 
 void intel_me_finalize_smm(void)
 {
-	struct me_hfs hfs;
-	u32 reg32;
+	union me_hfs hfs;
 
 	update_mei_base_address();
 
@@ -74,8 +73,7 @@ void intel_me_finalize_smm(void)
 		return;
 
 	/* Make sure ME is in a mode that expects EOP */
-	reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
-	memcpy(&hfs, &reg32, sizeof(u32));
+	hfs.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS);
 
 	/* Abort and leave device alone if not normal mode */
 	if (hfs.fpt_bad ||
diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c
index 52a68cee74..b12d052519 100644
--- a/src/southbridge/intel/bd82x6x/me_status.c
+++ b/src/southbridge/intel/bd82x6x/me_status.c
@@ -122,7 +122,7 @@ static const char *me_progress_policy_values[] = {
 	[0x10] = "Required VSCC values for flash parts do not match",
 };
 
-void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes)
+void intel_me_status(union me_hfs *hfs, union me_gmes *gmes)
 {
 	if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL < BIOS_DEBUG)
 		return;