i82801ix,bd82x6x,ibexpeak: rewrite expresscard hotplug

This implementation is more compact, unified and works with windows as well.

Tested under windows and under Debian GNU/Linux.

Change-Id: I585dec12e17e22d829baa3f2dc7aecc174f9d3b5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7296
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)

14 files changed, 256 insertions, 33 deletions

diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index 3d33edcd13..621a74341c 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -33,6 +33,7 @@ ramstage-y += usb_xhci.c
 ramstage-y += me.c
 ramstage-y += me_8.x.c
 ramstage-y += smbus.c
+ramstage-y += ../common/pciehp.c
 
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie.asl b/src/southbridge/intel/bd82x6x/acpi/pcie.asl
index 14ae449e7e..934cf782e9 100644
--- a/src/southbridge/intel/bd82x6x/acpi/pcie.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/pcie.asl
@@ -155,16 +155,6 @@ Device (RP03)
 	{
 		Return (IRQM (RPPN))
 	}
-#ifdef RP03_IS_EXPRESSCARD
-	Device (SLOT)
-	{
-		Name (_ADR, 0x00)
-		Method (_RMV, 0, NotSerialized)
-		{
-			Return (0x01)
-		}
-	}
-#endif
 }
 
 Device (RP04)
@@ -177,17 +167,6 @@ Device (RP04)
 	{
 		Return (IRQM (RPPN))
 	}
-
-#ifdef RP04_IS_EXPRESSCARD
-	Device (SLOT)
-	{
-		Name (_ADR, 0x00)
-		Method (_RMV, 0, NotSerialized)
-		{
-			Return (0x01)
-		}
-	}
-#endif
 }
 
 Device (RP05)
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index e5da531e75..d4adfd5c9f 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -100,6 +100,8 @@ struct southbridge_intel_bd82x6x_config {
 	int p_cnt_throttling_supported;
 	int c2_latency;
 	int docking_supported;
+
+	uint8_t pcie_hotplug_map[8];
 };
 
 #endif				/* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 80d6284629..3c559462ee 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -38,6 +38,7 @@
 #include <cpu/x86/smm.h>
 #include "pch.h"
 #include "nvs.h"
+#include <southbridge/intel/common/pciehp.h>
 
 #define NMI_OFF	0
 
@@ -838,6 +839,14 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_gpe1_blk.addrh = 0x0;
 }
 
+static void southbridge_fill_ssdt(void)
+{
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	config_t *chip = dev->chip_info;
+
+	intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
+}
+
 static struct pci_operations pci_ops = {
 	.set_subsystem = set_subsystem,
 };
@@ -848,6 +857,7 @@ static struct device_operations device_ops = {
 	.enable_resources	= pch_lpc_enable_resources,
 	.write_acpi_tables      = acpi_write_hpet,
 	.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
+	.acpi_fill_ssdt_generator = southbridge_fill_ssdt,
 	.init			= lpc_init,
 	.enable			= pch_lpc_enable,
 	.scan_bus		= scan_static_bus,
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index fadb43ff2b..4769dd53d0 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -23,6 +23,7 @@
 #include <device/pci.h>
 #include <device/pciexp.h>
 #include <device/pci_ids.h>
+#include <southbridge/intel/common/pciehp.h>
 #include "pch.h"
 
 static void pch_pcie_pm_early(struct device *dev)
@@ -218,6 +219,7 @@ static void pci_init(struct device *dev)
 {
 	u16 reg16;
 	u32 reg32;
+	struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
 
 	printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
 
@@ -255,6 +257,14 @@ static void pci_init(struct device *dev)
 	reg16 = pci_read_config16(dev, 0x1e);
 	//reg16 |= 0xf900;
 	pci_write_config16(dev, 0x1e, reg16);
+
+	/* Enable expresscard hotplug events.  */
+	if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
+		pci_write_config32(dev, 0xd8,
+				   pci_read_config32(dev, 0xd8)
+				   | (1 << 30));
+		pci_write_config16(dev, 0x42, 0x142);
+	}
 }
 
 static void pch_pcie_enable(device_t dev)
@@ -266,10 +276,15 @@ static void pch_pcie_enable(device_t dev)
 static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max)
 {
 	unsigned int ret;
+	struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
 
 	/* Normal PCIe Scan */
 	ret = pciexp_scan_bridge(dev, max);
 
+	if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
+		intel_acpi_pcie_hotplug_scan_slot(dev->link_list);
+	}
+
 	/* Late Power Management init after bridge device enumeration */
 	pch_pcie_pm_late(dev);
 
diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c
new file mode 100644
index 0000000000..5327c13923
--- /dev/null
+++ b/src/southbridge/intel/common/pciehp.c
@@ -0,0 +1,175 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include "pciehp.h"
+
+void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number)
+{
+	int port;
+	int have_hotplug = 0;
+
+	for (port = 0; port < port_number; port++) {
+		if (hotplug_map[port]) {
+			have_hotplug = 1;
+		}
+	}
+
+	if (!have_hotplug) {
+		return;
+	}
+
+	for (port = 0; port < port_number; port++) {
+		if (hotplug_map[port]) {
+			char scope_name[] = "\\_SB.PCI0.RP0x";
+			scope_name[sizeof("\\_SB.PCI0.RP0x") - 2] = '1' + port;
+			acpigen_write_scope(scope_name);
+
+			/*
+			  Device (SLOT)
+			  {
+			  	Name (_ADR, 0x00)
+			  	Method (_RMV, 0, NotSerialized)
+			  	{
+			  		Return (0x01)
+			  	}
+			  }
+			*/
+
+			acpigen_write_device("SLOT");
+
+			acpigen_write_name_byte("_ADR", 0x00);
+
+			acpigen_write_method("_RMV", 0);
+			/* ReturnOp  */
+			acpigen_emit_byte (0xa4);
+			/* One  */
+			acpigen_emit_byte (0x01);
+			acpigen_pop_len();
+			acpigen_pop_len();
+			acpigen_pop_len();
+		}
+	}
+
+	/* Method (_L01, 0, NotSerialized)
+	{
+		If (\_SB.PCI0.RP04.HPCS)
+		{
+			Sleep (100)
+			Store (0x01, \_SB.PCI0.RP04.HPCS)
+			If (\_SB.PCI0.RP04.PDC)
+			{
+				Store (0x01, \_SB.PCI0.RP04.PDC)
+				Notify (\_SB.PCI0.RP04, 0x00)
+			}
+		}
+	}
+
+	*/
+	acpigen_write_scope("\\_GPE");
+	acpigen_write_method("_L01", 0);
+	for (port = 0; port < port_number; port++) {
+		if (hotplug_map[port]) {
+			char reg_name[] = "\\_SB.PCI0.RP0x.HPCS";
+			reg_name[sizeof("\\_SB.PCI0.RP0x") - 2] = '1' + port;
+			acpigen_emit_byte(0xa0); /* IfOp. */
+			acpigen_write_len_f();
+			acpigen_emit_namestring(reg_name);
+
+			/* Sleep (100) */
+			acpigen_emit_byte(0x5b); /* SleepOp. */
+			acpigen_emit_byte(0x22);
+			acpigen_write_byte(100);
+
+			/* Store (0x01, \_SB.PCI0.RP04.HPCS) */
+			acpigen_emit_byte(0x70);
+			acpigen_emit_byte(0x01);
+			acpigen_emit_namestring(reg_name);
+
+			memcpy(reg_name + sizeof("\\_SB.PCI0.RP0x.") - 1, "PDC", 4);
+
+			/* If (\_SB.PCI0.RP04.PDC) */
+			acpigen_emit_byte(0xa0); /* IfOp. */
+			acpigen_write_len_f();
+			acpigen_emit_namestring(reg_name);
+
+			/* Store (0x01, \_SB.PCI0.RP04.PDC) */
+			acpigen_emit_byte(0x70);
+			acpigen_emit_byte(0x01);
+			acpigen_emit_namestring(reg_name);
+
+			reg_name[sizeof("\\_SB.PCI0.RP0x") - 1] = '\0';
+
+			/* Notify(\_SB.PCI0.RP04, 0x00) */
+			acpigen_emit_byte(0x86);
+			acpigen_emit_namestring(reg_name);
+			acpigen_emit_byte(0x00);
+			acpigen_pop_len();
+			acpigen_pop_len();
+		}
+	}
+	acpigen_pop_len();
+	acpigen_pop_len();
+
+}
+
+static void slot_dev_read_resources(struct device *dev)
+{
+	struct resource *resource;
+
+	resource = new_resource(dev, 0x10);
+	resource->size = 1 << 23;
+	resource->align = 22;
+	resource->gran = 22;
+	resource->limit = 0xffffffff;
+	resource->flags |= IORESOURCE_MEM;
+
+	resource = new_resource(dev, 0x14);
+	resource->size = 1 << 23;
+	resource->align = 22;
+	resource->gran = 22;
+	resource->limit = 0xffffffff;
+	resource->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
+
+	resource = new_resource(dev, 0x18);
+	resource->size = 1 << 12;
+	resource->align = 12;
+	resource->gran = 12;
+	resource->limit = 0xffff;
+	resource->flags |= IORESOURCE_IO;
+}
+
+static struct device_operations slot_dev_ops = {
+	.read_resources   = slot_dev_read_resources,
+};
+
+/* Add a dummy device to reserve I/O space for hotpluggable devices.  */
+void intel_acpi_pcie_hotplug_scan_slot(struct bus *bus)
+{
+	struct device *slot;
+	struct device_path slot_path = { .type = DEVICE_PATH_NONE };
+	slot = alloc_dev(bus, &slot_path);
+	slot->ops = &slot_dev_ops;
+}
diff --git a/src/southbridge/intel/common/pciehp.h b/src/southbridge/intel/common/pciehp.h
new file mode 100644
index 0000000000..7bf47f35a0
--- /dev/null
+++ b/src/southbridge/intel/common/pciehp.h
@@ -0,0 +1,2 @@
+void intel_acpi_pcie_hotplug_generator(u8 *hotplug_map, int port_number);
+void intel_acpi_pcie_hotplug_scan_slot(struct bus *bus);
diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc
index 4117263ee7..a6580c4208 100644
--- a/src/southbridge/intel/i82801ix/Makefile.inc
+++ b/src/southbridge/intel/i82801ix/Makefile.inc
@@ -27,6 +27,7 @@ ramstage-y += sata.c
 ramstage-y += hdaudio.c
 ramstage-y += thermal.c
 ramstage-y += smbus.c
+ramstage-y += ../common/pciehp.c
 
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
diff --git a/src/southbridge/intel/i82801ix/acpi/pcie.asl b/src/southbridge/intel/i82801ix/acpi/pcie.asl
index f02ad021c6..9233e5fa59 100644
--- a/src/southbridge/intel/i82801ix/acpi/pcie.asl
+++ b/src/southbridge/intel/i82801ix/acpi/pcie.asl
@@ -127,17 +127,6 @@ Device (RP04)
 		}
 
 	}
-
-#ifdef RP04_IS_EXPRESSCARD
-	Device (SLOT)
-	{
-		Name (_ADR, 0x00)
-		Method (_RMV, 0, NotSerialized)
-		{
-			Return (0x01)
-		}
-	}
-#endif
 }
 
 
diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h
index 5e1221d28b..b8b58a684b 100644
--- a/src/southbridge/intel/i82801ix/chip.h
+++ b/src/southbridge/intel/i82801ix/chip.h
@@ -88,6 +88,8 @@ struct southbridge_intel_i82801ix_config {
 		uint8_t value : 8;
 		uint8_t scale : 2;
 	} pcie_power_limits[6];
+
+	uint8_t pcie_hotplug_map[8];
 };
 
 #endif				/* SOUTHBRIDGE_INTEL_I82801IX_CHIP_H */
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index dc2cfe8ed7..e12c724c2d 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -36,6 +36,7 @@
 #include <string.h>
 #include "i82801ix.h"
 #include "nvs.h"
+#include <southbridge/intel/common/pciehp.h>
 
 #define NMI_OFF	0
 
@@ -555,6 +556,14 @@ static void southbridge_inject_dsdt(void)
 		acpigen_pop_len();
 	}
 }
+
+static void southbridge_fill_ssdt(void)
+{
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	config_t *chip = dev->chip_info;
+
+	intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
+}
 #endif
 
 static struct pci_operations pci_ops = {
@@ -568,6 +577,7 @@ static struct device_operations device_ops = {
 #if IS_ENABLED(CONFIG_PER_DEVICE_ACPI_TABLES)
 	.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
 	.write_acpi_tables      = acpi_write_hpet,
+	.acpi_fill_ssdt_generator = southbridge_fill_ssdt,
 #endif
 	.init			= lpc_init,
 	.scan_bus		= scan_static_bus,
diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c
index 2022dac3e7..7583715add 100644
--- a/src/southbridge/intel/i82801ix/pcie.c
+++ b/src/southbridge/intel/i82801ix/pcie.c
@@ -24,11 +24,14 @@
 #include <device/pci.h>
 #include <device/pciexp.h>
 #include <device/pci_ids.h>
+#include <southbridge/intel/common/pciehp.h>
+#include "chip.h"
 
 static void pci_init(struct device *dev)
 {
 	u16 reg16;
 	u32 reg32;
+	struct southbridge_intel_i82801ix_config *config = dev->chip_info;
 
 	printk(BIOS_DEBUG, "Initializing ICH9 PCIe root port.\n");
 
@@ -85,6 +88,14 @@ static void pci_init(struct device *dev)
 		reg32 |= (1 << 1);
 		pci_write_config32(dev, 0xe8, reg32);
 	}
+
+	/* Enable expresscard hotplug events.  */
+	if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
+		pci_write_config32(dev, 0xd8,
+				   pci_read_config32(dev, 0xd8)
+				   | (1 << 30));
+		pci_write_config16(dev, 0x42, 0x142);
+	}
 }
 
 static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
@@ -99,6 +110,21 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 	}
 }
 
+static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max)
+{
+	unsigned int ret;
+	struct southbridge_intel_i82801ix_config *config = dev->chip_info;
+
+	/* Normal PCIe Scan */
+	ret = pciexp_scan_bridge(dev, max);
+
+	if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
+		intel_acpi_pcie_hotplug_scan_slot(dev->link_list);
+	}
+
+	return ret;
+}
+
 static struct pci_operations pci_ops = {
 	.set_subsystem = pcie_set_subsystem,
 };
@@ -108,7 +134,7 @@ static struct device_operations device_ops = {
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_bus_enable_resources,
 	.init			= pci_init,
-	.scan_bus		= pciexp_scan_bridge,
+	.scan_bus		= pch_pciexp_scan_bridge,
 	.ops_pci		= &pci_ops,
 };
 
diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc
index 24cbe454a1..2db758a056 100644
--- a/src/southbridge/intel/ibexpeak/Makefile.inc
+++ b/src/southbridge/intel/ibexpeak/Makefile.inc
@@ -33,6 +33,7 @@ ramstage-y += me.c
 ramstage-y += ../bd82x6x/me_8.x.c
 ramstage-y += smbus.c
 ramstage-y += thermal.c
+ramstage-y += ../common/pciehp.c
 
 ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
 
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index c094ead557..03b40495e1 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -38,6 +38,7 @@
 #include <cpu/x86/smm.h>
 #include "pch.h"
 #include "nvs.h"
+#include <southbridge/intel/common/pciehp.h>
 
 #define NMI_OFF	0
 
@@ -821,6 +822,14 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 	fadt->x_gpe1_blk.addrh = 0x0;
 }
 
+static void southbridge_fill_ssdt(void)
+{
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	config_t *chip = dev->chip_info;
+
+	intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8);
+}
+
 static struct pci_operations pci_ops = {
 	.set_subsystem = set_subsystem,
 };
@@ -830,6 +839,7 @@ static struct device_operations device_ops = {
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pch_lpc_enable_resources,
 	.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
+	.acpi_fill_ssdt_generator = southbridge_fill_ssdt,
 	.write_acpi_tables      = acpi_write_hpet,
 	.init			= lpc_init,
 	.enable			= pch_lpc_enable,