diff options
author | Duncan Laurie <dlaurie@chromium.org> | 2014-10-14 08:37:18 -0700 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-02 13:24:28 +0200 |
commit | 2af67c9878bb84e10a6f526cfdeb2aacb76e119c (patch) | |
tree | 90e77c4cfa597600501a164938c9a6efc34d260b /src/southbridge/intel | |
parent | 4b2adb13f1432b0f05a94f1934071d2ec9dc297e (diff) |
broadwell: Add reporting of broadwell MCH revision
Since the E0 and F0 stepping parts have the same CPUID it is
necessary to use the MCH PCI device revision to determine what
the actual stepping is.
Add this decode table so the early output gives proper identification
of the installed CPU type.
BUG=chrome-os-partner:32359
BRANCH=samus,auron
TEST=build and boot on samus with E0 and F0 parts
Change-Id: Idce1e289cd958c77febc87395f27570247512a87
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: a5346141e45b105a35a7641f60b29e02ab2bdfa3
Original-Change-Id: I1bc127badd75ecc34d3d2dbae5d272bd4d9f9082
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/223158
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9228
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel')
0 files changed, 0 insertions, 0 deletions