diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-06-14 12:58:24 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-06-16 14:51:12 +0000 |
| commit | 17c89018a5084cad8ddc4e828b5fbb85f35c91ef (patch) | |
| tree | 63d7d3b29922a90c00ce703e8d7ac5ec4ef9b86f /src/southbridge/intel | |
| parent | c1328a6dba0b22c0cdbefe67d8db0bc5423bee84 (diff) | |
sb/intel/lynxpoint: Update xHCI _PS0 and _PS3 methods
Lynx Point PCH ACPI reference code version 1.9.1 has two additional
magic steps, which were already present in Broadwell. Add them.
Change-Id: Ia8ca6dcfcfb4ed6b0d957d249b93640ef74670d7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/xhci.asl | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/xhci.asl b/src/southbridge/intel/lynxpoint/acpi/xhci.asl index 9233163e3b..eec92c3fad 100644 --- a/src/southbridge/intel/lynxpoint/acpi/xhci.asl +++ b/src/southbridge/intel/lynxpoint/acpi/xhci.asl @@ -16,6 +16,14 @@ Device (XHCI) Offset (0x10), , 16, XMEM, 16, // MEM_BASE + Offset (0x40), + , 11, + SWAI, 1, + , 20, + Offset (0x44), + , 12, + SAIP, 2, + , 18, Offset (0x74), D0D3, 2, , 6, @@ -234,6 +242,12 @@ Device (XHCI) CLK2 = 1 #endif + // Clear PCI CFG offset 0x40[11] + ^SWAI = 0 + + // Clear PCI CFG offset 0x44[13:12] + ^SAIP = 0 + Return () } @@ -290,6 +304,12 @@ Device (XHCI) CLK2 = 0 #endif + // Set PCI CFG offset 0x40[11] + ^SWAI = 1 + + // Set PCI CFG offset 0x44[13:12] + ^SAIP = 1 + // Put device in D3 ^D0D3 = 3 |