diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2017-09-15 15:23:04 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-09-20 23:54:42 +0000 |
| commit | 0990fbf2d9b8a0070866788b185bdd4bf6e5537e (patch) | |
| tree | 85b2b519e9d0d5451fc1c63c93bcbdc4552e0cd2 /src/southbridge/intel | |
| parent | fe265a1b9ce7ad5b3dbd19f5857a902494bbe24e (diff) | |
vboot: reset vbnv in cmos when cmos failure occurs
There's an occasional issue on machines which use CMOS for their
vbnv storage. The machine that just powers up from complete G3
would have had their RTC rail not held up. The contents of vbnv
in CMOS could pass the crc8 though the values could be bad. In
order to fix this introduce two functions:
1. vbnv_init_cmos()
2. vbnv_cmos_failed()
At the start of vboot the CMOS is queried for failure. If there
is a failure indicated then the vbnv data is restored from flash
backup or reset to known values when there is no flash backup.
BUG=b:63054105
Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_pch_common.c | 6 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/pmutil.c | 6 |
2 files changed, 12 insertions, 0 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c index 0ea3dff001..f812247575 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_common.c +++ b/src/southbridge/intel/bd82x6x/early_pch_common.c @@ -22,6 +22,7 @@ #include <arch/acpi.h> #include <console/console.h> #include <rules.h> +#include <vboot/vbnv.h> #if ENV_ROMSTAGE uint64_t get_initial_timestamp(void) @@ -70,3 +71,8 @@ int rtc_failure(void) #endif return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD); } + +int vbnv_cmos_failed(void) +{ + return rtc_failure(); +} diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 642d5befd0..55fe403495 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -24,6 +24,7 @@ #include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> +#include <vboot/vbnv.h> #include "pch.h" #if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) @@ -563,3 +564,8 @@ int rtc_failure(void) #endif return !!(pci_read_config8(dev, GEN_PMCON_3) & RTC_BATTERY_DEAD); } + +int vbnv_cmos_failed(void) +{ + return rtc_failure(); +} |