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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-05-26 19:53:29 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-06-14 23:54:51 +0200 |
| commit | d450609145a78c2d93707664073466bf29c83426 (patch) | |
| tree | 61ec843b9fc69b43f28bec215d53ebc0fcfb77f0 /src/southbridge/intel | |
| parent | 579fdb4910aaac3e29f55b44f5333b4a9416d3be (diff) | |
Added CL7 support
according to "JEDEC_DDR2_SPD_Specification_Rev1.3.pdf"
Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3)
page 16 and page 60, CL7 support added
Change-Id: I22aaf064ab8767755f74dfdb44e32d13fc61b2c4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/14976
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
0 files changed, 0 insertions, 0 deletions