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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-01-06 10:41:41 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-01-07 10:39:58 +0000
commitb544c000565f928813299d0ea19dcae88ac7961e (patch)
tree47576651cc111dc0996392d6f9d510e98dd68415 /src/southbridge/intel
parent438f86166325e4f8089be5c65b40075d77a0406c (diff)
intel/lynxpoint: Fix spelling
Change-Id: I684e1962a9d4312ee9fad4ada70323b02ca3ae48 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/30687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/lynxpoint/bootblock.c2
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 20d0ee3342..1a9e7bba61 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -54,7 +54,7 @@ static void map_rcba(void)
static void enable_port80_on_lpc(void)
{
- /* Enable port 80 POST on LPC. The chipset does this by deafult,
+ /* Enable port 80 POST on LPC. The chipset does this by default,
* but it doesn't appear to hurt anything. */
u32 gcs = RCBA32(GCS);
gcs = gcs & ~0x4;
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 10f57f543e..474c7df32c 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -660,7 +660,7 @@ static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value,
{
/*
* Check if the register is enabled. If so and the base exceeds the
- * device's deafult claim range add the resoure.
+ * device's default, claim range and add the resource.
*/
if (reg_value & 1) {
u16 base = reg_value & 0xfffc;