diff options
| author | Nico Huber <nico.h@gmx.de> | 2013-06-18 22:36:34 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-06-19 17:58:55 +0200 |
| commit | 9359f2de0033cfb47fab01b2c73ae36408281fbb (patch) | |
| tree | 94a20e54d13a6bad408be1507b37d09963e026b4 /src/southbridge/intel | |
| parent | 414b9478518836ce72084edba1c3a51b0a745d0c (diff) | |
intel/i82801gx: Store initial timestamp
Upgrade the ICH7 bootblock to store an initial timestamp like we do it
since Sandy Brigde. I've checked the datasheets for the used scratchpad
registers and grepped for their usage. I'm pretty sure that they aren't
used on any ICH7 based board (for anything before the usual S3-resume
indication).
Change-Id: I28a9b90d3e6f6401a8114ecd240554a5dddc0eb5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3498
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/i82801gx/bootblock.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index b352fcad03..153a456cb6 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -18,6 +18,18 @@ */ #include <arch/io.h> +#include <cpu/x86/tsc.h> + +static void store_initial_timestamp(void) +{ + /* On i945/ICH7 we have two 32bit scratchpad registers available: + * D0:F0 0xdc (SKPAD) + * D31:F2 0xd0 (SATA SP) + */ + tsc_t tsc = rdtsc(); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); + pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); +} static void enable_spi_prefetch(void) { @@ -34,6 +46,9 @@ static void enable_spi_prefetch(void) static void bootblock_southbridge_init(void) { +#if CONFIG_COLLECT_TIMESTAMPS + store_initial_timestamp(); +#endif enable_spi_prefetch(); } |