summaryrefslogtreecommitdiff
path: root/src/southbridge/intel
diff options
context:
space:
mode:
authorDuncan Laurie <dlaurie@chromium.org>2012-12-17 11:24:45 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-14 18:24:27 +0100
commit51254049b91a816c53b5cadf72d254f11e882818 (patch)
tree0235b9b6a1476d8a569fee65ce61787dad916dbd /src/southbridge/intel
parentdf7be71374a8b80708c58fd13e26b9e3fc6ed54c (diff)
haswell: Add ULT CPUID and updated microcode
This adds microcode ffff000a and the CPUIDs for ULT. Change-Id: I341c1148a355d8373b31032b9f209232bd03230a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2647 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge/intel')
0 files changed, 0 insertions, 0 deletions