summaryrefslogtreecommitdiff
path: root/src/southbridge/intel
diff options
context:
space:
mode:
authorMartin Roth <martinroth@google.com>2016-07-28 16:32:56 -0600
committerStefan Reinauer <stefan.reinauer@coreboot.org>2016-08-01 21:43:56 +0200
commitbb9722bd775d575401edff14a9b80406ecbd974a (patch)
tree7e16eb11f2681aeccbce658d4cac6a3510578528 /src/southbridge/intel
parent049b46270d63c47db75b27246555c904e42fe9e2 (diff)
Add newlines at the end of all coreboot files
Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15974 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl b/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl
index 6997c07422..431c61e74e 100644
--- a/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/lpt_lp.asl
@@ -86,4 +86,4 @@ Scope (\_SB.PCI0.LPCB)
Store (0x1, GIOS) // INPUT
Store (0x1, GINV) // INVERT
}
-} \ No newline at end of file
+}