Revert "CMOS: Add set_option and rework get_option."

This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660.

Stepan pointed out that "s" means string, which makes the following statement
in this commit message invalid: "Since we either have reserved space (which
we shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go."

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

8 files changed, 22 insertions, 22 deletions

diff --git a/src/southbridge/intel/esb6300/esb6300_lpc.c b/src/southbridge/intel/esb6300/esb6300_lpc.c
index 9b90545384..52db05b6a4 100644
--- a/src/southbridge/intel/esb6300/esb6300_lpc.c
+++ b/src/southbridge/intel/esb6300/esb6300_lpc.c
@@ -277,7 +277,7 @@ static void lpc_init(struct device *dev)
 {
 	uint8_t byte;
 	uint32_t value;
-	uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_FAIL;
+	int pwr_on=MAINBOARD_POWER_ON_AFTER_FAIL;
 
 	/* sata settings */
 	pci_write_config32(dev, 0x58, 0x00001181);
@@ -326,7 +326,7 @@ static void lpc_init(struct device *dev)
 
 	esb6300_enable_lpc(dev);
 
-        get_option("power_on_after_fail", &pwr_on);
+        get_option(&pwr_on, "power_on_after_fail");
 	byte = pci_read_config8(dev, 0xa4);
 	byte &= 0xfe;
 	if (!pwr_on) {
diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/i3100_lpc.c
index 04314775d7..8e0c460880 100644
--- a/src/southbridge/intel/i3100/i3100_lpc.c
+++ b/src/southbridge/intel/i3100/i3100_lpc.c
@@ -297,7 +297,7 @@ static void i3100_gpio_init(device_t dev)
 static void lpc_init(struct device *dev)
 {
 	u8 byte;
-	uint32_t pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL;
+	int pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL;
 
 	setup_ioapic(dev);
 
@@ -306,7 +306,7 @@ static void lpc_init(struct device *dev)
 
 	i3100_enable_serial_irqs(dev);
 
-	get_option("power_on_after_fail", &pwr_on);
+	get_option(&pwr_on, "power_on_after_fail");
 	byte = pci_read_config8(dev, 0xa4);
 	byte &= 0xfe;
 	if (!pwr_on) {
diff --git a/src/southbridge/intel/i82801ca/i82801ca_lpc.c b/src/southbridge/intel/i82801ca/i82801ca_lpc.c
index 2327c01150..b249438a1f 100644
--- a/src/southbridge/intel/i82801ca/i82801ca_lpc.c
+++ b/src/southbridge/intel/i82801ca/i82801ca_lpc.c
@@ -88,7 +88,7 @@ void i82801ca_rtc_init(struct device *dev)
 {
     uint32_t dword;
     int rtc_failed;
-    uint32_t pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
     uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
 
     rtc_failed = pmcon3 & RTC_BATTERY_DEAD;
@@ -99,7 +99,7 @@ void i82801ca_rtc_init(struct device *dev)
         pmcon3 &= ~RTC_POWER_FAILED;
     }
 
-    get_option("power_on_after_fail", &pwr_on);
+    get_option(&pwr_on, "power_on_after_fail");
 	pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
 	if (!pwr_on) {
 		pmcon3 |= SLEEP_AFTER_POWER_FAIL;
@@ -158,7 +158,7 @@ static void lpc_init(struct device *dev)
 {
 	uint8_t byte;
 	int pwr_on=-1;
-	uint32_t nmi_option;
+	int nmi_option;
 
 	/* IO APIC initialization */
 	i82801ca_enable_ioapic(dev);
@@ -186,7 +186,7 @@ static void lpc_init(struct device *dev)
     outb(byte, 0x61);
     byte = inb(0x70);
     nmi_option = NMI_OFF;
-    get_option("nmi", &nmi_option);
+    get_option(&nmi_option, "nmi");
     if (nmi_option) {			
         byte &= ~(1 << 7); /* set NMI */
         outb(byte, 0x70);
diff --git a/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c b/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c
index 2a96c424f4..cec09192b7 100644
--- a/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c
+++ b/src/southbridge/intel/i82801dbm/i82801dbm_lpc.c
@@ -119,7 +119,7 @@ static void lpc_init(struct device *dev)
 {
 	uint8_t byte;
 	int pwr_on=-1;
-	uint32_t nmi_option;
+	int nmi_option;
 
 	/* IO APIC initialization */
 	i82801dbm_enable_ioapic(dev);
@@ -159,7 +159,7 @@ static void lpc_init(struct device *dev)
     outb(byte, 0x61);
     byte = inb(0x70);
 	nmi_option = NMI_OFF;
-	get_option("nmi", &nmi_option);
+	get_option(&nmi_option, "nmi");
 	if (nmi_option) {			
         byte &= ~(1 << 7); /* set NMI */
         outb(byte, 0x70);
diff --git a/src/southbridge/intel/i82801er/i82801er_lpc.c b/src/southbridge/intel/i82801er/i82801er_lpc.c
index f679a722d9..02d474e8d5 100644
--- a/src/southbridge/intel/i82801er/i82801er_lpc.c
+++ b/src/southbridge/intel/i82801er/i82801er_lpc.c
@@ -283,7 +283,7 @@ static void lpc_init(struct device *dev)
 {
 	uint8_t byte;
 	uint32_t value;
-	uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
 
 	/* IO APIC initialization */
 	value = pci_read_config32(dev, 0xd0);
@@ -303,7 +303,7 @@ static void lpc_init(struct device *dev)
 	/* Clear SATA to non raid */
 	pci_write_config8(dev, 0xae, 0x00);
 
-        get_option("power_on_after_fail", &pwr_on);
+        get_option(&pwr_on, "power_on_after_fail");
 	byte = pci_read_config8(dev, 0xa4);
 	byte &= 0xfe;
 	if (!pwr_on) {
diff --git a/src/southbridge/intel/i82801gx/i82801gx_lpc.c b/src/southbridge/intel/i82801gx/i82801gx_lpc.c
index 29546348b1..241d610bdd 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_lpc.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_lpc.c
@@ -185,14 +185,14 @@ static void i82801gx_power_options(device_t dev)
 	u8 reg8;
 	u16 reg16;
 
-	uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
-	uint32_t nmi_option;
+	int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int nmi_option;
 
 	/* Which state do we want to goto after g3 (power restored)?
 	 * 0 == S0 Full On
 	 * 1 == S5 Soft Off
 	 */
-        get_option("power_on_after_fail", &pwr_on);
+        get_option(&pwr_on, "power_on_after_fail");
 	reg8 = pci_read_config8(dev, GEN_PMCON_3);
 	reg8 &= 0xfe;
 	if (pwr_on) {
@@ -216,7 +216,7 @@ static void i82801gx_power_options(device_t dev)
 
 	reg8 = inb(0x70);
 	nmi_option = NMI_OFF;
-	get_option("nmi", &nmi_option);
+	get_option(&nmi_option, "nmi");
 	if (nmi_option) {
 		printk_info ("NMI sources enabled.\n");
 		reg8 &= ~(1 << 7);	/* Set NMI. */
diff --git a/src/southbridge/intel/i82801xx/i82801xx_lpc.c b/src/southbridge/intel/i82801xx/i82801xx_lpc.c
index a9d4e9d1ac..cdc809f3bc 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_lpc.c
+++ b/src/southbridge/intel/i82801xx/i82801xx_lpc.c
@@ -180,7 +180,7 @@ static void i82801xx_power_options(device_t dev)
 {
 	uint8_t byte;
 	int pwr_on = -1;
-	uint32_t nmi_option;
+	int nmi_option;
 
 	/* power after power fail */
 	/* FIXME this doesn't work! */
@@ -199,7 +199,7 @@ static void i82801xx_power_options(device_t dev)
 	byte = inb(0x70);
 
 	nmi_option = NMI_OFF;
-	get_option("nmi", &nmi_option);
+	get_option(&nmi_option, "nmi");
 	if (nmi_option) {
 		byte &= ~(1 << 7);	/* Set NMI. */
 		outb(byte, 0x70);
diff --git a/src/southbridge/intel/pxhd/pxhd_bridge.c b/src/southbridge/intel/pxhd/pxhd_bridge.c
index fadbd15491..5913063606 100644
--- a/src/southbridge/intel/pxhd/pxhd_bridge.c
+++ b/src/southbridge/intel/pxhd/pxhd_bridge.c
@@ -38,12 +38,12 @@ static void pxhd_enable(device_t dev)
 
 static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max)
 {
-	uint32_t bus_100Mhz = 0;
+	int bus_100Mhz = 0;
 
 	dev->link[0].dev = dev;
 	dev->links = 1;
 
-	get_option("pxhd_bus_speed_100", &bus_100Mhz);
+	get_option(&bus_100Mhz, "pxhd_bus_speed_100");
 	if(bus_100Mhz) {
 		uint16_t word;
 
@@ -66,7 +66,7 @@ static void pcix_init(device_t dev)
 	uint32_t dword;
 	uint16_t word;
 	uint8_t byte;
-	uint32_t nmi_option;
+	int nmi_option;
 
 	/* Bridge control ISA enable */
 	pci_write_config8(dev, 0x3e, 0x07);
@@ -115,7 +115,7 @@ static void pcix_init(device_t dev)
  	
 	/* NMI enable */
 	nmi_option = NMI_OFF;
-	get_option("nmi", &nmi_option);
+	get_option(&nmi_option, "nmi");
 	if(nmi_option) {
 		dword = pci_read_config32(dev, 0x44);
         	dword |= (1<<0);