diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-08 00:52:02 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-09 23:54:18 +0000 |
| commit | 6065ead9c56970b50054ce4da53b13d37cba3ef2 (patch) | |
| tree | 817676fd1488ec46cd13bb3457ee0b2fd65845ec /src/southbridge/intel | |
| parent | c9e42b98ef227193181d57b1c126da4a2a13e69a (diff) | |
sb/intel/bd82x6x/acpi/lpc.asl: Drop dead code
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Idc600d7a1ce1e47ea4c361caf2b32f1faa56e0f7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43265
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/lpc.asl | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl index 4591bb06ec..4b101d2190 100644 --- a/src/southbridge/intel/bd82x6x/acpi/lpc.asl +++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl @@ -173,7 +173,6 @@ Device (LPCB) IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI - //IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH7-M ACPI IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH7-M GPIO }) |