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authorFelix Held <felix-coreboot@felixheld.de>2020-12-09 02:18:00 +0100
committerFelix Held <felix-coreboot@felixheld.de>2020-12-10 01:22:06 +0000
commit5d7fa16c5c7e625371a1fcffedff99027f8b35d8 (patch)
tree65eda617570febc8eb63ff408e86f95f5143d626 /src/southbridge/intel
parent1e63e361c68eda9c4876de24416880ab83ec29d9 (diff)
soc/amd/picasso/reset: use port and bit defines from cf9_reset.h
The register name and the name of one bit are slightly different, but have the same functionality. Change-Id: I025f1c7b2c7643afe245f2275ae6ef45e64b951a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48487 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
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