sb/intel/*/lpc.c: Don't try to write read-only PCICMD bits

For all these southbridges, the lower nibble of PCICMD is read-only.

Tested on Asrock B85M Pro4 (Lynxpoint-H), LPC's PCICMD does not change.

Change-Id: Ib3b16b1b9651f7f3bd06ff8bc27dafd8a323e93c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

7 files changed, 0 insertions, 35 deletions

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index df5625afa5..a498f870a0 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -519,11 +519,6 @@ static void lpc_init(struct device *dev)
 	/* Print detected platform */
 	report_pch_info(dev);
 
-	/* Set the value for PCI command register. */
-	pci_write_config16(dev, PCI_COMMAND,
-			   PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
-			   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-
 	/* IO APIC initialization. */
 	pch_enable_ioapic(dev);
 
diff --git a/src/southbridge/intel/i82801dx/lpc.c b/src/southbridge/intel/i82801dx/lpc.c
index dec12666fc..f207c11556 100644
--- a/src/southbridge/intel/i82801dx/lpc.c
+++ b/src/southbridge/intel/i82801dx/lpc.c
@@ -252,11 +252,6 @@ static void enable_hpet(struct device *dev)
 
 static void lpc_init(struct device *dev)
 {
-	/* Set the value for PCI command register. */
-	pci_write_config16(dev, PCI_COMMAND,
-			   PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
-			   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-
 	i82801dx_enable_acpi(dev);
 	/* IO APIC initialization. */
 	i82801dx_enable_ioapic(dev);
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index eb59eb031c..721735cb15 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -341,11 +341,6 @@ static void lpc_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "i82801gx: %s\n", __func__);
 
-	/* Set the value for PCI command register. */
-	pci_write_config16(dev, PCI_COMMAND,
-			   PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
-			   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-
 	/* IO APIC initialization. */
 	i82801gx_enable_ioapic(dev);
 
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index ad7141ac49..652da54103 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -355,11 +355,6 @@ static void lpc_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "i82801ix: %s\n", __func__);
 
-	/* Set the value for PCI command register. */
-	pci_write_config16(dev, PCI_COMMAND,
-			   PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
-			   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-
 	/* IO APIC initialization. */
 	i82801ix_enable_apic(dev);
 
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index 2f7b516a2a..1f4cf29187 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -347,11 +347,6 @@ static void lpc_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "i82801jx: %s\n", __func__);
 
-	/* Set the value for PCI command register. */
-	pci_write_config16(dev, PCI_COMMAND,
-			   PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
-			   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-
 	/* IO APIC initialization. */
 	i82801jx_enable_apic(dev);
 
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 8269dd9f22..dddecd79d0 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -433,11 +433,6 @@ static void lpc_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "pch: %s\n", __func__);
 
-	/* Set the value for PCI command register. */
-	pci_write_config16(dev, PCI_COMMAND,
-			   PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
-			   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-
 	/* IO APIC initialization. */
 	pch_enable_ioapic(dev);
 
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 4286e6ca0a..2872a0b556 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -505,11 +505,6 @@ static void lpc_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "pch: %s\n", __func__);
 
-	/* Set the value for PCI command register. */
-	pci_write_config16(dev, PCI_COMMAND,
-			   PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
-			   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
-
 	/* IO APIC initialization. */
 	pch_enable_ioapic(dev);