diff options
| author | Zhongze Hu <frankhu@google.com> | 2018-02-16 00:53:02 -0800 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2018-02-23 22:04:41 +0000 |
| commit | 12f656ced7469fffc6ba1f7befcea593894b0935 (patch) | |
| tree | 44d77919191ce25a3767a7c549380fc0971ab6a7 /src/southbridge/intel | |
| parent | 4ecd42f9b52cd01b659c21f62e5ca2e79f5da4ab (diff) | |
mb/google/fizz: Enable PCIe port 11, 12
Our CFM daughter card would like to use individual PCIe lanes for two
different devices on the card.
dlaurie@ has reconfigured PCIe port 9-12 from 1x4 to 1x2 + 2x1 on b2b
connector on fizz to meet the requirement:
https://chrome-internal-review.googlesource.com/571936
We also need to enable the ports on device tree.
BUG=b:72523836
TEST=none
BRANCH=fizz
Change-Id: Icded9850d833752680e0174b6c476e657817b319
Reviewed-on: https://chromium-review.googlesource.com/923867
Commit-Ready: Zhongze Hu <frankhu@google.com>
Tested-by: Zhongze Hu <frankhu@google.com>
Reviewed-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/924860
Commit-Queue: Shelley Chen <shchen@chromium.org>
Tested-by: Shelley Chen <shchen@chromium.org>
Signed-off-by: Zhongze Hu <frankhu@chromium.org>
Reviewed-on: https://review.coreboot.org/23845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/southbridge/intel')
0 files changed, 0 insertions, 0 deletions