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authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-12-29 05:12:56 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-20 09:24:35 +0000
commit780e02d1a54598f60f290e7eaba3c0456006ecce (patch)
tree334397f52b6f0d3edf300eb1fcf8c15415631ed5 /src/southbridge/intel
parentc196246f75ae8fd235055250593fc7a78f5f3888 (diff)
ACPI GNVS: Drop APIC, factor out MPEN
APIC was not referenced anywhere in ASL. MPEN has references under boards: getac/p470, roda/rk9, roda/rk886ex. MPEN has reference also in Intel SpeedStep ASL. Replace static MPEN with detection of multiple CPUs installed. Change-Id: Ib5f06416b23196b7227ccd5814162925c31c084b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/acpi/globalnvs.asl4
-rw-r--r--src/southbridge/intel/bd82x6x/include/soc/nvs.h4
-rw-r--r--src/southbridge/intel/bd82x6x/lpc.c8
-rw-r--r--src/southbridge/intel/i82801gx/acpi/globalnvs.asl2
-rw-r--r--src/southbridge/intel/i82801gx/include/soc/nvs.h2
-rw-r--r--src/southbridge/intel/i82801gx/lpc.c4
-rw-r--r--src/southbridge/intel/i82801ix/acpi/globalnvs.asl2
-rw-r--r--src/southbridge/intel/i82801ix/include/soc/nvs.h2
-rw-r--r--src/southbridge/intel/i82801ix/lpc.c8
-rw-r--r--src/southbridge/intel/i82801jx/acpi/globalnvs.asl4
-rw-r--r--src/southbridge/intel/i82801jx/include/soc/nvs.h4
-rw-r--r--src/southbridge/intel/ibexpeak/acpi/globalnvs.asl4
-rw-r--r--src/southbridge/intel/ibexpeak/include/soc/nvs.h4
-rw-r--r--src/southbridge/intel/ibexpeak/lpc.c8
-rw-r--r--src/southbridge/intel/lynxpoint/acpi/globalnvs.asl4
-rw-r--r--src/southbridge/intel/lynxpoint/include/soc/nvs.h4
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c8
17 files changed, 30 insertions, 46 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
index c6c7397031..23b6769bed 100644
--- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
@@ -53,8 +53,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TMPS, 8, // 0x25 - Temperature Sensor ID
/* Processor Identification */
Offset (0x28),
- APIC, 8, // 0x28 - APIC Enabled by coreboot
- MPEN, 8, // 0x29 - Multi Processor Enable
+ , 8, // 0x28 - Enabled by coreboot
+ , 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1
PPCM, 8, // 0x2c - Max. PPC state
diff --git a/src/southbridge/intel/bd82x6x/include/soc/nvs.h b/src/southbridge/intel/bd82x6x/include/soc/nvs.h
index 25e5b6edac..969d59209b 100644
--- a/src/southbridge/intel/bd82x6x/include/soc/nvs.h
+++ b/src/southbridge/intel/bd82x6x/include/soc/nvs.h
@@ -44,8 +44,8 @@ struct __packed global_nvs {
u8 tmps; /* 0x25 - Temperature Sensor ID */
u8 rsvd3[2];
/* Processor Identification */
- u8 apic; /* 0x28 - APIC enabled */
- u8 mpen; /* 0x29 - MP capable/enabled */
+ u8 unused_was_apic; /* 0x28 - APIC enabled */
+ u8 unused_was_mpen; /* 0x29 - MP capable/enabled */
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
u8 ppcm; /* 0x2c - Max. PPC state */
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index a351bc3900..d5d39f5ff6 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -12,7 +12,6 @@
#include <arch/io.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
-#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <cpu/x86/smm.h>
#include <string.h>
@@ -24,7 +23,6 @@
#include <southbridge/intel/common/pmutil.h>
#include <southbridge/intel/common/rtc.h>
#include <southbridge/intel/common/spi.h>
-#include <soc/nvs.h>
#define NMI_OFF 0
@@ -641,12 +639,6 @@ static void pch_lpc_enable(struct device *dev)
pch_enable(dev);
}
-void soc_fill_gnvs(struct global_nvs *gnvs)
-{
- gnvs->apic = 1;
- gnvs->mpen = 1; /* Enable Multi Processing */
-}
-
static const char *lpc_acpi_name(const struct device *dev)
{
return "LPCB";
diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
index 9b8fd1187d..8bd222fbc1 100644
--- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl
@@ -52,7 +52,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
B2SS, 8, // 0x24 - BAT2 stored status
/* Processor Identification */
Offset (0x28),
- APIC, 8, // 0x28 - APIC Enabled by coreboot
+ , 8, // 0x28 - Enabled by coreboot
MPEN, 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1
diff --git a/src/southbridge/intel/i82801gx/include/soc/nvs.h b/src/southbridge/intel/i82801gx/include/soc/nvs.h
index cfb44fde7a..d9e01df05e 100644
--- a/src/southbridge/intel/i82801gx/include/soc/nvs.h
+++ b/src/southbridge/intel/i82801gx/include/soc/nvs.h
@@ -40,7 +40,7 @@ struct __packed global_nvs {
u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */
u8 rsvd3[3];
/* Processor Identification */
- u8 apic; /* 0x28 - APIC enabled */
+ u8 unused_was_apic; /* 0x28 - APIC enabled */
u8 mpen; /* 0x29 - MP capable/enabled */
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 4b7898c75e..6c48e9c906 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -466,8 +466,8 @@ static void lpc_final(struct device *dev)
void soc_fill_gnvs(struct global_nvs *gnvs)
{
- gnvs->apic = 1;
- gnvs->mpen = 1; /* Enable Multi Processing */
+ /* MPEN, Enable Multi Processing. */
+ gnvs->mpen = dev_count_cpu() > 1 ? 1 : 0;
}
static const char *lpc_acpi_name(const struct device *dev)
diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
index 5687eb0e0b..021de14e2c 100644
--- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl
@@ -53,7 +53,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
B2SS, 8, // 0x24 - BAT2 stored status
/* Processor Identification */
Offset (0x28),
- APIC, 8, // 0x28 - APIC Enabled by coreboot
+ , 8, // 0x28 - Enabled by coreboot
MPEN, 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1
diff --git a/src/southbridge/intel/i82801ix/include/soc/nvs.h b/src/southbridge/intel/i82801ix/include/soc/nvs.h
index e8150dcc86..4fa56763bc 100644
--- a/src/southbridge/intel/i82801ix/include/soc/nvs.h
+++ b/src/southbridge/intel/i82801ix/include/soc/nvs.h
@@ -40,7 +40,7 @@ struct __packed global_nvs {
u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */
u8 rsvd3[3];
/* Processor Identification */
- u8 apic; /* 0x28 - APIC enabled */
+ u8 unused_was_apic; /* 0x28 - APIC enabled */
u8 mpen; /* 0x29 - MP capable/enabled */
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index b84b458027..5400237fa8 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -12,6 +12,7 @@
#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h>
#include <acpi/acpigen.h>
#include <string.h>
@@ -20,6 +21,7 @@
#include <southbridge/intel/common/pciehp.h>
#include <southbridge/intel/common/pmutil.h>
#include <southbridge/intel/common/acpi_pirq_gen.h>
+#include <soc/nvs.h>
#define NMI_OFF 0
@@ -450,6 +452,12 @@ static void i82801ix_lpc_read_resources(struct device *dev)
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
+void soc_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* MPEN, Enable Multi Processing. */
+ gnvs->mpen = dev_count_cpu() > 1 ? 1 : 0;
+}
+
static const char *lpc_acpi_name(const struct device *dev)
{
return "LPCB";
diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
index 5687eb0e0b..3d0d3b2790 100644
--- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
@@ -53,8 +53,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
B2SS, 8, // 0x24 - BAT2 stored status
/* Processor Identification */
Offset (0x28),
- APIC, 8, // 0x28 - APIC Enabled by coreboot
- MPEN, 8, // 0x29 - Multi Processor Enable
+ , 8, // 0x28 - Enabled by coreboot
+ , 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1
PPCM, 8, // 0x2c - Max. PPC state
diff --git a/src/southbridge/intel/i82801jx/include/soc/nvs.h b/src/southbridge/intel/i82801jx/include/soc/nvs.h
index d2de581aa7..4325a8c1ee 100644
--- a/src/southbridge/intel/i82801jx/include/soc/nvs.h
+++ b/src/southbridge/intel/i82801jx/include/soc/nvs.h
@@ -39,8 +39,8 @@ struct __packed global_nvs {
u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */
u8 rsvd3[3];
/* Processor Identification */
- u8 apic; /* 0x28 - APIC enabled */
- u8 mpen; /* 0x29 - MP capable/enabled */
+ u8 unused_was_apic; /* 0x28 - APIC enabled */
+ u8 unused_was_mpen; /* 0x29 - MP capable/enabled */
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
u8 ppcm; /* 0x2c - Max. PPC state */
diff --git a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
index 314141e65f..174d12f3c7 100644
--- a/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
+++ b/src/southbridge/intel/ibexpeak/acpi/globalnvs.asl
@@ -53,8 +53,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TMPS, 8, // 0x25 - Temperature Sensor ID
/* Processor Identification */
Offset (0x28),
- APIC, 8, // 0x28 - APIC Enabled by coreboot
- MPEN, 8, // 0x29 - Multi Processor Enable
+ , 8, // 0x28 - Enabled by coreboot
+ , 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1
PPCM, 8, // 0x2c - Max. PPC state
diff --git a/src/southbridge/intel/ibexpeak/include/soc/nvs.h b/src/southbridge/intel/ibexpeak/include/soc/nvs.h
index 42d588fdc6..5ce88a68b1 100644
--- a/src/southbridge/intel/ibexpeak/include/soc/nvs.h
+++ b/src/southbridge/intel/ibexpeak/include/soc/nvs.h
@@ -45,8 +45,8 @@ struct __packed global_nvs {
u8 tmps; /* 0x25 - Temperature Sensor ID */
u8 rsvd3[2];
/* Processor Identification */
- u8 apic; /* 0x28 - APIC enabled */
- u8 mpen; /* 0x29 - MP capable/enabled */
+ u8 unused_was_apic; /* 0x28 - APIC enabled */
+ u8 unused_was_mpen; /* 0x29 - MP capable/enabled */
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
u8 ppcm; /* 0x2c - Max. PPC state */
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index e4d64fd78b..361d3a977b 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -13,7 +13,6 @@
#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
-#include <acpi/acpi_gnvs.h>
#include <elog.h>
#include <acpi/acpigen.h>
#include <string.h>
@@ -23,7 +22,6 @@
#include <southbridge/intel/common/pciehp.h>
#include <southbridge/intel/common/acpi_pirq_gen.h>
#include <southbridge/intel/common/spi.h>
-#include <soc/nvs.h>
#define NMI_OFF 0
@@ -541,12 +539,6 @@ static void pch_lpc_enable(struct device *dev)
pch_enable(dev);
}
-void soc_fill_gnvs(struct global_nvs *gnvs)
-{
- gnvs->apic = 1;
- gnvs->mpen = 1; /* Enable Multi Processing */
-}
-
static const char *lpc_acpi_name(const struct device *dev)
{
return "LPCB";
diff --git a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
index 249954d857..758667d02d 100644
--- a/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/globalnvs.asl
@@ -54,8 +54,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
TMPS, 8, // 0x25 - Temperature Sensor ID
/* Processor Identification */
Offset (0x28),
- APIC, 8, // 0x28 - APIC Enabled by coreboot
- MPEN, 8, // 0x29 - Multi Processor Enable
+ , 8, // 0x28 - Enabled by coreboot
+ , 8, // 0x29 - Multi Processor Enable
PCP0, 8, // 0x2a - PDC CPU/CORE 0
PCP1, 8, // 0x2b - PDC CPU/CORE 1
PPCM, 8, // 0x2c - Max. PPC state
diff --git a/src/southbridge/intel/lynxpoint/include/soc/nvs.h b/src/southbridge/intel/lynxpoint/include/soc/nvs.h
index 8027fe4b98..17ded13589 100644
--- a/src/southbridge/intel/lynxpoint/include/soc/nvs.h
+++ b/src/southbridge/intel/lynxpoint/include/soc/nvs.h
@@ -44,8 +44,8 @@ struct __packed global_nvs {
u8 tmps; /* 0x25 - Temperature Sensor ID */
u8 rsvd3[2];
/* Processor Identification */
- u8 apic; /* 0x28 - APIC enabled */
- u8 mpen; /* 0x29 - MP capable/enabled */
+ u8 unused_was_apic; /* 0x28 - APIC enabled */
+ u8 unused_was_mpen; /* 0x29 - MP capable/enabled */
u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */
u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */
u8 ppcm; /* 0x2c - Max. PPC state */
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 2624aa9150..24a5a7ef9a 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -11,7 +11,6 @@
#include <arch/io.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
-#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h>
#include <string.h>
#include "chip.h"
@@ -21,7 +20,6 @@
#include <southbridge/intel/common/acpi_pirq_gen.h>
#include <southbridge/intel/common/rtc.h>
#include <southbridge/intel/common/spi.h>
-#include <soc/nvs.h>
#define NMI_OFF 0
@@ -679,12 +677,6 @@ static void pch_lpc_enable(struct device *dev)
pch_enable(dev);
}
-void soc_fill_gnvs(struct global_nvs *gnvs)
-{
- gnvs->apic = 1;
- gnvs->mpen = 1; /* Enable Multi Processing */
-}
-
static const char *lpc_acpi_name(const struct device *dev)
{
return "LPCB";
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 11:57:24 +0000