diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2013-03-21 11:51:41 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-22 00:00:09 +0100 |
| commit | 24d1d4b47274eb82893e6726472a991a36fce0aa (patch) | |
| tree | 57126316330f6f9d407f605fa831ce530650f069 /src/southbridge/intel | |
| parent | 55ed3106556a9bcbe36d3389dc5230d4a4ee2a40 (diff) | |
x86: Unify arch/io.h and arch/romcc_io.h
Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.
Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.
Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
45 files changed, 5 insertions, 59 deletions
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 7f4f577cd6..85a940e2de 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/x86/tsc.h> #include "pch.h" diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 5b266cc10c..670e1cedf5 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -21,7 +21,6 @@ #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c index a626649e2b..9de97e7fe2 100644 --- a/src/southbridge/intel/bd82x6x/early_smbus.c +++ b/src/southbridge/intel/bd82x6x/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/bd82x6x/early_spi.c b/src/southbridge/intel/bd82x6x/early_spi.c index ddfc4c2261..6f57f637a9 100644 --- a/src/southbridge/intel/bd82x6x/early_spi.c +++ b/src/southbridge/intel/bd82x6x/early_spi.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index bbe792f908..f4e526d85f 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index be6d480a62..bcc2f3dad9 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/post_codes.h> #include <northbridge/intel/sandybridge/pcie_config.c> #include "pch.h" diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c index 25eda9a74c..39241d6094 100644 --- a/src/southbridge/intel/bd82x6x/gpio.c +++ b/src/southbridge/intel/bd82x6x/gpio.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include "pch.h" #include "gpio.h" diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index b9aff37d5c..7fdf9261f8 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -38,7 +38,6 @@ #include <elog.h> #ifdef __SMM__ -# include <arch/romcc_io.h> # include <northbridge/intel/sandybridge/pcie_config.c> #else # include <device/device.h> diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index b71f7ea12f..f79adf59c0 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -38,7 +38,6 @@ #include <elog.h> #ifdef __SMM__ -# include <arch/romcc_io.h> # include <northbridge/intel/sandybridge/pcie_config.c> #else # include <device/device.h> diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index f2c7dc1648..37a0b6422c 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -23,7 +23,6 @@ #include <delay.h> #ifdef __SMM__ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #else /* !__SMM__ */ #include <device/device.h> diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 5d5dad1460..545e268a9c 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -22,7 +22,6 @@ #include <types.h> #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c index 4303dd0e7a..09169b1bc8 100644 --- a/src/southbridge/intel/bd82x6x/spi.c +++ b/src/southbridge/intel/bd82x6x/spi.c @@ -34,7 +34,6 @@ #define min(a, b) ((a)<(b)?(a):(b)) #ifdef __SMM__ -#include <arch/romcc_io.h> #include <northbridge/intel/sandybridge/pcie_config.c> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pcie_read_config8(dev, reg) diff --git a/src/southbridge/intel/bd82x6x/usb_debug.c b/src/southbridge/intel/bd82x6x/usb_debug.c index 607a88c6c0..79a43bd308 100644 --- a/src/southbridge/intel/bd82x6x/usb_debug.c +++ b/src/southbridge/intel/bd82x6x/usb_debug.c @@ -25,7 +25,6 @@ #include "pch.h" #ifdef __PRE_RAM__ -#include <arch/romcc_io.h> void enable_usbdebug(unsigned int port) { u32 dbgctl; diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c index 135cbc0609..b350bde6a9 100644 --- a/src/southbridge/intel/i82371eb/bootblock.c +++ b/src/southbridge/intel/i82371eb/bootblock.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_ids.h> #include "i82371eb.h" diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c index aaf86114e9..a2f055bca7 100644 --- a/src/southbridge/intel/i82371eb/early_pm.c +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <console/console.h> diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index d0abcf4dfb..80a4de9f80 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801ax/early_smbus.c b/src/southbridge/intel/i82801ax/early_smbus.c index dde9f33933..716652a0f4 100644 --- a/src/southbridge/intel/i82801ax/early_smbus.c +++ b/src/southbridge/intel/i82801ax/early_smbus.c @@ -21,7 +21,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801bx/early_smbus.c b/src/southbridge/intel/i82801bx/early_smbus.c index 0522e497b3..26c9e85059 100644 --- a/src/southbridge/intel/i82801bx/early_smbus.c +++ b/src/southbridge/intel/i82801bx/early_smbus.c @@ -21,7 +21,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index ca453a103c..6f4d4f8846 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 1d306da280..61ac901df5 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -21,7 +21,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index fc052068e8..b352fcad03 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> static void enable_spi_prefetch(void) { diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c index 7744e719dc..b11e4fa16a 100644 --- a/src/southbridge/intel/i82801gx/early_smbus.c +++ b/src/southbridge/intel/i82801gx/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 9d71fa3362..f199b84b65 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -21,7 +21,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/i82801gx/usb_debug.c b/src/southbridge/intel/i82801gx/usb_debug.c index d5a743c28b..f447f7bb84 100644 --- a/src/southbridge/intel/i82801gx/usb_debug.c +++ b/src/southbridge/intel/i82801gx/usb_debug.c @@ -17,9 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef __PRE_RAM__ +#define __PRE_RAM__ // Use simple device model for this file even in ramstage +#endif #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <usbdebug.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index fc052068e8..b352fcad03 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> static void enable_spi_prefetch(void) { diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c index c25c2349ae..0514719344 100644 --- a/src/southbridge/intel/i82801ix/dmi_setup.c +++ b/src/southbridge/intel/i82801ix/dmi_setup.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <console/console.h> #include <northbridge/intel/gm45/gm45.h> diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index af2e63f67e..8849cfa2c8 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include "i82801ix.h" void i82801ix_early_init(void) diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c index 74b36e6ba5..226afac2d7 100644 --- a/src/southbridge/intel/i82801ix/early_smbus.c +++ b/src/southbridge/intel/i82801ix/early_smbus.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 4e8edfe615..913223b0ab 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -22,7 +22,6 @@ #include <types.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 2770d55cad..96291189cd 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -18,7 +18,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <cpu/x86/tsc.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c index e41b801a8b..6b61eac3db 100644 --- a/src/southbridge/intel/lynxpoint/early_me.c +++ b/src/southbridge/intel/lynxpoint/early_me.c @@ -21,7 +21,6 @@ #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <delay.h> #include <device/pci_ids.h> diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 3709aed63b..a390d737bc 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <device/pci_def.h> #include <elog.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c index a626649e2b..9de97e7fe2 100644 --- a/src/southbridge/intel/lynxpoint/early_smbus.c +++ b/src/southbridge/intel/lynxpoint/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/lynxpoint/early_spi.c b/src/southbridge/intel/lynxpoint/early_spi.c index ddfc4c2261..6f57f637a9 100644 --- a/src/southbridge/intel/lynxpoint/early_spi.c +++ b/src/southbridge/intel/lynxpoint/early_spi.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index b2e009123e..ebd5c2c50a 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c index 2cece13e17..d9bc22531c 100644 --- a/src/southbridge/intel/lynxpoint/finalize.c +++ b/src/southbridge/intel/lynxpoint/finalize.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/post_codes.h> #include <spi-generic.h> #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/gpio.c b/src/southbridge/intel/lynxpoint/gpio.c index 9d36887dd1..b492068ccd 100644 --- a/src/southbridge/intel/lynxpoint/gpio.c +++ b/src/southbridge/intel/lynxpoint/gpio.c @@ -20,14 +20,8 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> - -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif - #include "pch.h" #include "gpio.h" diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index 2d2e0576ea..a6e4f5c998 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -20,12 +20,8 @@ #include <stdint.h> #include <string.h> #include <arch/io.h> -#ifdef __PRE_RAM__ -#include <arch/romcc_io.h> -#else #include <device/device.h> #include <device/pci.h> -#endif #include "pch.h" #include "lp_gpio.h" diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 2e790fc2a5..a16879b757 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -31,19 +31,14 @@ #include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> +#include <device/device.h> +#include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_def.h> #include <string.h> #include <delay.h> #include <elog.h> -#ifdef __SMM__ -# include <arch/romcc_io.h> -#else -# include <device/device.h> -# include <device/pci.h> -#endif - #include "me.h" #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 49f7df8d52..203a1bbfb5 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -23,7 +23,6 @@ #include <types.h> #include <arch/hlt.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/lynxpoint/spi.c b/src/southbridge/intel/lynxpoint/spi.c index 123c6a9d62..eaa17d5e21 100644 --- a/src/southbridge/intel/lynxpoint/spi.c +++ b/src/southbridge/intel/lynxpoint/spi.c @@ -34,7 +34,6 @@ #define min(a, b) ((a)<(b)?(a):(b)) #ifdef __SMM__ -#include <arch/romcc_io.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/lynxpoint/usb_debug.c b/src/southbridge/intel/lynxpoint/usb_debug.c index 1cee353e2d..d8da7b5484 100644 --- a/src/southbridge/intel/lynxpoint/usb_debug.c +++ b/src/southbridge/intel/lynxpoint/usb_debug.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <usbdebug.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/sch/early_smbus.c b/src/southbridge/intel/sch/early_smbus.c index 9a015041c0..8adc04df47 100644 --- a/src/southbridge/intel/sch/early_smbus.c +++ b/src/southbridge/intel/sch/early_smbus.c @@ -19,7 +19,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c index 99ae018770..bbaf4bb7f9 100644 --- a/src/southbridge/intel/sch/smihandler.c +++ b/src/southbridge/intel/sch/smihandler.c @@ -20,7 +20,6 @@ */ #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> diff --git a/src/southbridge/intel/sch/usb_debug.c b/src/southbridge/intel/sch/usb_debug.c index 1986258d7c..4189716c08 100644 --- a/src/southbridge/intel/sch/usb_debug.c +++ b/src/southbridge/intel/sch/usb_debug.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <arch/io.h> -#include <arch/romcc_io.h> #include <console/console.h> #include <usbdebug.h> #include <device/pci_def.h> |