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| author | Keith Hui <buurin@gmail.com> | 2024-04-15 23:14:56 -0400 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-04-18 11:04:25 +0000 |
| commit | f5b993de4fcf9b1153681e64285139e69e2c87cd (patch) | |
| tree | 700fb1fbb6749b56b9d535419f64e56c2d888b89 /src/southbridge/intel | |
| parent | 8b5aacca3f2c16fc4153887a6289e2c3eca9d10d (diff) | |
sio/nuvoton/nct6779d: Correct GPIOBASE virtual LDN
According to datasheet, the enable bit for direct I/O access to GPIO
lines is at CR30[3] of LDN 8, not [0] as currently coded.
Change-Id: Id2f997aebc36a2fcaa8c3763f324d3b288f785d2
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81926
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
0 files changed, 0 insertions, 0 deletions