diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-28 14:27:46 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-06 09:08:15 +0000 |
| commit | b70ff52b83d5ffe9feca95d086a5366dd6f6ce4d (patch) | |
| tree | cb78016240a6c4cd35905230d7f0f807eedbe91e /src/southbridge/intel | |
| parent | ca935d1107ccc3ba77cc6915360f17f38e2f328d (diff) | |
intel: Define `RCBA_LENGTH` in Kconfig and use it
Change-Id: Ief81d49f04c1743b2a37633c4a35da9d6ddb0974
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50039
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/acpi/pch.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/common/Kconfig | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/ich7.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/acpi/ich9.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801jx/acpi/ich10.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/acpi/pch.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/lpc.c | 2 |
7 files changed, 10 insertions, 6 deletions
diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 8833a5ed2e..5a80ab0b3e 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -181,7 +181,7 @@ Scope(\) // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 5b5fe554e1..1bdefd4b93 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -108,6 +108,10 @@ config FIXED_RCBA_MMIO_BASE hex default 0xfed1c000 +config RCBA_LENGTH + hex + default 0x4000 + config FIXED_SMBUS_IO_BASE hex depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS diff --git a/src/southbridge/intel/i82801gx/acpi/ich7.asl b/src/southbridge/intel/i82801gx/acpi/ich7.asl index 4f55277445..6c9c9694f9 100644 --- a/src/southbridge/intel/i82801gx/acpi/ich7.asl +++ b/src/southbridge/intel/i82801gx/acpi/ich7.asl @@ -110,7 +110,7 @@ Scope(\) // ICH7 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field(RCRB, DWordAcc, Lock, Preserve) { // Backbone diff --git a/src/southbridge/intel/i82801ix/acpi/ich9.asl b/src/southbridge/intel/i82801ix/acpi/ich9.asl index 3455acf981..1a07ec211c 100644 --- a/src/southbridge/intel/i82801ix/acpi/ich9.asl +++ b/src/southbridge/intel/i82801ix/acpi/ich9.asl @@ -110,7 +110,7 @@ Scope(\) // ICH9 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone diff --git a/src/southbridge/intel/i82801jx/acpi/ich10.asl b/src/southbridge/intel/i82801jx/acpi/ich10.asl index 53ead1c967..0e4c03b07a 100644 --- a/src/southbridge/intel/i82801jx/acpi/ich10.asl +++ b/src/southbridge/intel/i82801jx/acpi/ich10.asl @@ -112,7 +112,7 @@ Scope(\) // ICH10 Root Complex Register Block. Memory Mapped through RCBA) - OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) + OperationRegion(RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field(RCRB, DWordAcc, Lock, Preserve) { Offset(0x0000), // Backbone diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index f97a5ad58d..50f73cdf9c 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -19,7 +19,7 @@ Scope (\) } // Root Complex Register Block - OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000) + OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH) Field (RCRB, DWordAcc, Lock, Preserve) { Offset (0x3404), // High Performance Timer Configuration diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 20b9b4318f..b0ff5450cf 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -560,7 +560,7 @@ static void pch_lpc_add_mmio_resources(struct device *dev) if (CONFIG_FIXED_RCBA_MMIO_BASE < default_decode_base) { res = new_resource(dev, RCBA); res->base = (resource_t)CONFIG_FIXED_RCBA_MMIO_BASE; - res->size = 16 * 1024; + res->size = CONFIG_RCBA_LENGTH; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; } |