diff options
| author | Gerd Hoffmann <kraxel@redhat.com> | 2013-09-17 09:49:02 +0200 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-10-01 18:31:42 +0200 |
| commit | b142a5154280c00a3e4bc9d162b31bfe4b665f60 (patch) | |
| tree | a557bde8cfe28de7ec3f873d2e9c464f70903662 /src/southbridge/intel | |
| parent | c371442a2925e9bfc9ddc045bfd446db53f0a145 (diff) | |
qemu: q35: avoid address conflict
Qemu has the fw_cfg interface at 0x510, which conflicts with
power management base address in coreboot. Move the pmbase to a
non-conflicting address. No need to worry about speedstep, it
is not supported by qemu and isn't enabled in the qemu config.
Change-Id: I3e87d8301988028ca0ea7d96c08b4e26ac15a7c2
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3938
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/i82801ix/i82801ix.h | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index ca28107313..d84af3abe7 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -29,7 +29,16 @@ #define DEFAULT_TBAR 0xfed1b000 #define DEFAULT_RCBA 0xfed1c000 -#define DEFAULT_PMBASE 0x00000500 /* Speedstep code has this hardcoded, too. */ +#ifdef CONFIG_BOARD_EMULATION_QEMU_X86_Q35 +/* + * Qemu has the fw_cfg interface at 0x510. Move the pmbase to a + * non-conflicting address. No need to worry about speedstep, it + * is not supported by qemu and isn't enabled in the qemu config. + */ +# define DEFAULT_PMBASE 0x00000600 +#else +# define DEFAULT_PMBASE 0x00000500 /* Speedstep code has this hardcoded, too. */ +#endif #define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) #define DEFAULT_GPIOBASE 0x00000580 |