diff options
| author | Jakub Czapiga <jacz@semihalf.com> | 2022-02-15 11:50:31 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-08 16:06:33 +0000 |
| commit | ad6157ebdfddc39b95e388487e00cadd2bbf368b (patch) | |
| tree | bbb85c9b13faf74515387ee8978eefd6d79e6b06 /src/southbridge/intel | |
| parent | e96ade6981c60af4d6f24471d7f6a440ab7bfd4e (diff) | |
timestamps: Rename timestamps to make names more consistent
This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/bd82x6x/early_me.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c index 561bed9664..866996f913 100644 --- a/src/southbridge/intel/bd82x6x/early_me.c +++ b/src/southbridge/intel/bd82x6x/early_me.c @@ -166,7 +166,7 @@ int intel_early_me_init_done(u8 status) "ME: ME is reporting as disabled, " "so not waiting for a response.\n"); } else { - timestamp_add_now(TS_ME_INFORM_DRAM_WAIT); + timestamp_add_now(TS_ME_INFORM_DRAM_START); udelay(100); millisec = 0; do { @@ -177,7 +177,7 @@ int intel_early_me_init_done(u8 status) millisec++; } while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK) && (millisec <= 5000)); - timestamp_add_now(TS_ME_INFORM_DRAM_DONE); + timestamp_add_now(TS_ME_INFORM_DRAM_END); } me_fws2 = pci_read_config32(PCH_ME_DEV, PCI_ME_GMES); |