diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-21 15:56:13 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-06-27 17:38:20 +0000 |
| commit | 741508bb3e82ced370ee00c44e69ca77beebfb1a (patch) | |
| tree | 16825dc9b47c2799e308e7eea82028793799c2ca /src/southbridge/intel | |
| parent | 3fc2dc444ed5624089729f94b8ac7fc8fb49eb11 (diff) | |
sb/intel/i82801gx/fadt.c: Reorder statements
Change the order of the assignments to match that of i82801ix. This
changes the binary but the effective result should be the same.
Change-Id: Id720fce40e751295e629585d34017f10af2b5c7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42651
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/i82801gx/fadt.c | 59 |
1 files changed, 29 insertions, 30 deletions
diff --git a/src/southbridge/intel/i82801gx/fadt.c b/src/southbridge/intel/i82801gx/fadt.c index 1324a78a46..7c35d44af2 100644 --- a/src/southbridge/intel/i82801gx/fadt.c +++ b/src/southbridge/intel/i82801gx/fadt.c @@ -15,6 +15,16 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) struct southbridge_intel_i82801gx_config *chip = dev->chip_info; u16 pmbase = lpc_get_pmbase(); + fadt->sci_int = 0x9; + + if (permanent_smi_handler()) { + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->pstate_cnt = APM_CNT_PST_CONTROL; + fadt->cst_cnt = APM_CNT_CST_CONTROL; + } + fadt->pm1a_evt_blk = pmbase; fadt->pm1b_evt_blk = 0x0; fadt->pm1a_cnt_blk = pmbase + PM1_CNT; @@ -31,6 +41,25 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->gpe0_blk_len = 8; fadt->gpe1_blk_len = 0; fadt->gpe1_base = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = chip->c3_latency; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + if (chip->p_cnt_throttling_supported) + fadt->duty_width = 3; + else + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x32; + fadt->iapc_boot_arch = 0x03; + fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED + | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE + | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER + | ACPI_FADT_C2_MP_SUPPORTED); + if (chip->docking_supported) + fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; fadt->reset_reg.space_id = 1; fadt->reset_reg.bit_width = 8; @@ -96,34 +125,4 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->x_gpe1_blk.access_size = 0; fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x32; - - fadt->sci_int = 0x9; - - if (permanent_smi_handler()) { - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->pstate_cnt = APM_CNT_PST_CONTROL; - fadt->cst_cnt = APM_CNT_CST_CONTROL; - } - - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = chip->c3_latency; - fadt->flush_size = 0; - fadt->flush_stride = 0; - fadt->duty_offset = 1; - if (chip->p_cnt_throttling_supported) - fadt->duty_width = 3; - else - fadt->duty_width = 0; - fadt->iapc_boot_arch = 0x03; - fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED - | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE - | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER - | ACPI_FADT_C2_MP_SUPPORTED); - if (chip->docking_supported) - fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; } |