Revert "model_206ax: Use parallel MP init"

This reverts commit 5fbe788bae15f0d24d56011e8eb8b48c107b7b05.
This commit was submitted without its parent being submitted,
resulting in coreboot not building.

Change-Id: I87497093ccf6909b88e3a40d5f472afeb7f2c552
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

4 files changed, 4 insertions, 28 deletions

diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c
index 96098facb1..814ff80598 100644
--- a/src/southbridge/intel/bd82x6x/elog.c
+++ b/src/southbridge/intel/bd82x6x/elog.c
@@ -22,7 +22,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <elog.h>
-#include <southbridge/intel/common/pmutils.h>
+#include "pch.h"
 
 void pch_log_state(void)
 {
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 9e87ff6b72..ebcb058c0b 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -68,6 +68,9 @@ int pch_silicon_revision(void);
 int pch_silicon_type(void);
 int pch_silicon_supported(int type, int rev);
 void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
+#if IS_ENABLED(CONFIG_ELOG)
+void pch_log_state(void);
+#endif
 #else /* __PRE_RAM__ */
 void enable_smbus(void);
 void enable_usb_bar(void);
diff --git a/src/southbridge/intel/common/pmutil.h b/src/southbridge/intel/common/pmutil.h
index 4aa2812ff1..e2b6e5828d 100644
--- a/src/southbridge/intel/common/pmutil.h
+++ b/src/southbridge/intel/common/pmutil.h
@@ -123,6 +123,5 @@ void southbridge_update_gnvs(u8 apm_cnt, int *smm_done);
 void southbridge_finalize_all(void);
 void southbridge_smi_monitor(void);
 em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd);
-void pch_log_state(void);
 
 #endif /*INTEL_COMMON_PMUTIL_H */
diff --git a/src/southbridge/intel/common/smi.c b/src/southbridge/intel/common/smi.c
index 264b5487d8..deaecb2625 100644
--- a/src/southbridge/intel/common/smi.c
+++ b/src/southbridge/intel/common/smi.c
@@ -159,29 +159,3 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
 		  "d" (APM_CNT)
 	);
 }
-
-void southbridge_smm_clear_state(void)
-{
-	u32 smi_en;
-
-	if (IS_ENABLED(CONFIG_ELOG))
-	/* Log events from chipset before clearing */
-		pch_log_state();
-
-	printk(BIOS_DEBUG, "Initializing Southbridge SMI...");
-	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", get_pmbase());
-
-	smi_en = inl(get_pmbase() + SMI_EN);
-	if (smi_en & APMC_EN) {
-		printk(BIOS_INFO, "SMI# handler already enabled?\n");
-		return;
-	}
-
-	printk(BIOS_DEBUG, "\n");
-
-	/* Dump and clear status registers */
-	reset_smi_status();
-	reset_pm1_status();
-	reset_tco_status();
-	reset_gpe0_status();
-}