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| author | Kevin Chiu <kevin.chiu.17802@gmail.com> | 2021-11-14 22:51:08 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-11-16 02:52:22 +0000 |
| commit | 2ec91a37bcced48b5cbd7bf349dec38df0c3a58b (patch) | |
| tree | 599d331eabb625f626769b580daaceaa551dab6d /src/southbridge/intel | |
| parent | da0c4f42f608a94014ccf51df5b04a6a86e4315f (diff) | |
mb/google/brya/var/vell: Generate LP5 RAM ID
Add the support LP5 RAM parts for vell:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
BUG=b:204284866
TEST=emerge-brya coreboot
Change-Id: I49745948ebdb25fd98e285defd75714f80271968
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Diffstat (limited to 'src/southbridge/intel')
0 files changed, 0 insertions, 0 deletions