diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2012-04-20 17:11:31 +0300 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2012-04-24 00:02:12 +0200 |
| commit | 1d89f14355e72d6969c8b8aae56904ebee965d43 (patch) | |
| tree | 169a3e35a259b958b59e3fa6041e695bf203edac /src/southbridge/intel | |
| parent | 0a19ddc36d9df98ab4b29c36359cc5274d4d9f57 (diff) | |
Intel 82801dx: compile early_smbus as separate object
Add early_smbus.c for romstage-y list and remove respective
include on mainboard romstage.c files.
Tested on AOpen board.
Change-Id: I1c7e6cb32e3a9d7cc9b6037dc27e59149d492001
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/909
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/i82801dx/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801dx/early_smbus.c | 26 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801dx/i82801dx.h | 5 |
3 files changed, 14 insertions, 19 deletions
diff --git a/src/southbridge/intel/i82801dx/Makefile.inc b/src/southbridge/intel/i82801dx/Makefile.inc index 9070158d0d..9644210b53 100644 --- a/src/southbridge/intel/i82801dx/Makefile.inc +++ b/src/southbridge/intel/i82801dx/Makefile.inc @@ -31,3 +31,5 @@ ramstage-y += reset.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +romstage-y += early_smbus.c diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c index 00eaee0f9e..1387525f3b 100644 --- a/src/southbridge/intel/i82801dx/early_smbus.c +++ b/src/southbridge/intel/i82801dx/early_smbus.c @@ -18,26 +18,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "i82801dx.h" +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_def.h> +#include <console/console.h> -#define SMBHSTSTAT 0x0 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -/* Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -//#define SMBUS_TIMEOUT (100*1000*10) +#include "i82801dx.h" -static void enable_smbus(void) +void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); @@ -112,7 +100,7 @@ static int smbus_wait_until_done(void) return loops ? 0 : -3; } -static int smbus_read_byte(unsigned device, unsigned address) +int smbus_read_byte(unsigned device, unsigned address) { unsigned char global_status_register; unsigned char byte; diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index a38c793eda..4da430a395 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -31,9 +31,14 @@ #ifndef I82801DX_H #define I82801DX_H +#if !defined(__ASSEMBLER__) && !defined(__ROMCC__) #if !defined(__PRE_RAM__) #include "chip.h" extern void i82801dx_enable(device_t dev); +#else +void enable_smbus(void); +int smbus_read_byte(unsigned device, unsigned address); +#endif #endif /* |