diff options
| author | Yuchi Chen <yuchi.chen@intel.com> | 2024-11-06 09:05:20 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-11-14 19:55:04 +0000 |
| commit | 1a22344d58657f144171bb419828ca4733cb93a6 (patch) | |
| tree | 3acdfec38ce3ec14aa0b4595be66695be939a71c /src/southbridge/intel | |
| parent | 618fbe0d210d50275492521a7c31a04202ef9a7e (diff) | |
southbridge/intel/common: Improve ACPI _PRT method generation
Add a scope parameter for `intel_write_pci0_PRT()` so that it could be
reused for multiple domains.
Change-Id: I867a0c74e633ddfe63d29870f9fd50ca883c2e78
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85013
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/southbridge/intel')
| -rw-r--r-- | src/southbridge/intel/common/acpi_pirq_gen.c | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/common/acpi_pirq_gen.h | 5 | ||||
| -rw-r--r-- | src/southbridge/intel/common/rcba_pirq.c | 2 |
3 files changed, 6 insertions, 9 deletions
diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c index 1dadc8e6db..3b5c3e58d0 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.c +++ b/src/southbridge/intel/common/acpi_pirq_gen.c @@ -43,12 +43,10 @@ static void gen_pic_route(const struct slot_pin_irq_map *pin_irq_map, } } -void intel_write_pci0_PRT(const struct slot_pin_irq_map *pin_irq_map, - unsigned int map_count, - const struct pic_pirq_map *pirq_map) +void intel_write_pci_PRT(const char *scope, const struct slot_pin_irq_map *pin_irq_map, + unsigned int map_count, const struct pic_pirq_map *pirq_map) { - /* \_SB.PCI0._PRT */ - acpigen_write_scope("\\_SB.PCI0"); + acpigen_write_scope(scope); acpigen_write_method("_PRT", 0); acpigen_write_if(); acpigen_emit_namestring("PICM"); diff --git a/src/southbridge/intel/common/acpi_pirq_gen.h b/src/southbridge/intel/common/acpi_pirq_gen.h index 36e432e31c..f22e1d4dfc 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.h +++ b/src/southbridge/intel/common/acpi_pirq_gen.h @@ -84,9 +84,8 @@ struct pic_pirq_map { * slot/pin combination, and optionally providing paths to LNKx devices that can * provide IRQs in PIC mode. */ -void intel_write_pci0_PRT(const struct slot_pin_irq_map *pin_irq_map, - unsigned int map_count, - const struct pic_pirq_map *pirq_map); +void intel_write_pci_PRT(const char *scope, const struct slot_pin_irq_map *pin_irq_map, + unsigned int map_count, const struct pic_pirq_map *pirq_map); bool is_slot_pin_assigned(const struct slot_pin_irq_map *pin_irq_map, unsigned int map_count, unsigned int slot, diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index 956fe633da..ae22143364 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -90,7 +90,7 @@ void intel_acpi_gen_def_acpi_pirq(const struct device *lpc) map_count++; } - intel_write_pci0_PRT(pin_irq_map, map_count, &pirq_map); + intel_write_pci_PRT("\\_SB.PCI0", pin_irq_map, map_count, &pirq_map); free(pin_irq_map); } |