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authorJohanna Schander <coreboot@mimoja.de>2020-01-04 15:14:59 +0100
committerPatrick Georgi <pgeorgi@google.com>2020-02-01 19:51:51 +0000
commit0174ea78bf51fc5f7c6261449835bf621de448b2 (patch)
tree54b4314f90aecdfaed8b1b19e569f149cc57c2c5 /src/southbridge/intel
parenta58e5034426f657491550ccc6d6d2423e4cdb45f (diff)
util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems
This GPIO dumping was implemented using the Document Number: 341080-001 IntelĀ® 495 Series Chipset Family On-Package Platform Controller Hub Volume 1 of 2 datasheet. The GPIO community ports can be found in table 36-1, while the community and pin descriptions are taken from linux/pinctrl/intel/pinctrl-icelake.c . This commit was tested on the late 2019 Razer Blade Stealth with 1065G7 and Chipset 495 PCH and the output manually compared against linux/pinctrl-intel. Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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