Auto-declare chip_operations

The name is derived directly from the device path.

Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>

12 files changed, 0 insertions, 19 deletions

diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 07a2af7b9c..05eeab225d 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -79,6 +79,4 @@ struct southbridge_intel_bd82x6x_config {
 	uint8_t pcie_port_coalesce;
 };
 
-extern struct chip_operations southbridge_intel_bd82x6x_ops;
-
 #endif				/* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */
diff --git a/src/southbridge/intel/esb6300/chip.h b/src/southbridge/intel/esb6300/chip.h
index 4082769cce..c6dc3a36ee 100644
--- a/src/southbridge/intel/esb6300/chip.h
+++ b/src/southbridge/intel/esb6300/chip.h
@@ -26,5 +26,4 @@ struct southbridge_intel_esb6300_config
 	unsigned int  pirq_a_d;
 	unsigned int  pirq_e_h;
 };
-extern struct chip_operations southbridge_intel_esb6300_ops;
 
diff --git a/src/southbridge/intel/i3100/chip.h b/src/southbridge/intel/i3100/chip.h
index 7e58674daf..21d3a46591 100644
--- a/src/southbridge/intel/i3100/chip.h
+++ b/src/southbridge/intel/i3100/chip.h
@@ -47,4 +47,3 @@ struct southbridge_intel_i3100_config
 	u32 pirq_a_d;
 	u32 pirq_e_h;
 };
-extern struct chip_operations southbridge_intel_i3100_ops;
diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h
index 1cb2929346..80846930c5 100644
--- a/src/southbridge/intel/i82371eb/chip.h
+++ b/src/southbridge/intel/i82371eb/chip.h
@@ -23,8 +23,6 @@
 
 #include <device/device.h>
 
-extern const struct chip_operations southbridge_intel_i82371eb_ops;
-
 struct southbridge_intel_i82371eb_config {
 	int ide0_enable:1;
 	int ide0_drive0_udma33_enable:1;
diff --git a/src/southbridge/intel/i82801ax/chip.h b/src/southbridge/intel/i82801ax/chip.h
index 21b6f9fcf3..989f35b917 100644
--- a/src/southbridge/intel/i82801ax/chip.h
+++ b/src/southbridge/intel/i82801ax/chip.h
@@ -37,6 +37,4 @@ struct southbridge_intel_i82801ax_config {
 	u8 ide1_enable;
 };
 
-extern struct chip_operations southbridge_intel_i82801ax_ops;
-
 #endif
diff --git a/src/southbridge/intel/i82801bx/chip.h b/src/southbridge/intel/i82801bx/chip.h
index 5cdfc5da50..987eb8f8b2 100644
--- a/src/southbridge/intel/i82801bx/chip.h
+++ b/src/southbridge/intel/i82801bx/chip.h
@@ -41,6 +41,4 @@ struct southbridge_intel_i82801bx_config {
 	u8 ide1_enable;
 };
 
-extern struct chip_operations southbridge_intel_i82801bx_ops;
-
 #endif
diff --git a/src/southbridge/intel/i82801cx/chip.h b/src/southbridge/intel/i82801cx/chip.h
index 88415e0556..56185213eb 100644
--- a/src/southbridge/intel/i82801cx/chip.h
+++ b/src/southbridge/intel/i82801cx/chip.h
@@ -4,6 +4,5 @@
 struct southbridge_intel_i82801cx_config
 {
 };
-extern struct chip_operations southbridge_intel_i82801cx_ops;
 
 #endif /* I82801CX_CHIP_H */
diff --git a/src/southbridge/intel/i82801dx/chip.h b/src/southbridge/intel/i82801dx/chip.h
index 1209ec854b..42701f778f 100644
--- a/src/southbridge/intel/i82801dx/chip.h
+++ b/src/southbridge/intel/i82801dx/chip.h
@@ -41,6 +41,4 @@ struct southbridge_intel_i82801dx_config {
 	uint8_t ide1_enable;
 };
 
-extern struct chip_operations southbridge_intel_i82801dx_ops;
-
 #endif				/* I82801DBM_CHIP_H */
diff --git a/src/southbridge/intel/i82801ex/chip.h b/src/southbridge/intel/i82801ex/chip.h
index f04fc3fd29..891fa16d15 100644
--- a/src/southbridge/intel/i82801ex/chip.h
+++ b/src/southbridge/intel/i82801ex/chip.h
@@ -30,7 +30,6 @@ struct southbridge_intel_i82801ex_config
 	unsigned int  pirq_a_d;
 	unsigned int  pirq_e_h;
 };
-extern struct chip_operations southbridge_intel_i82801ex_ops;
 
 #endif /* I82801EX_CHIP_H */
 
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h
index cc17539d7d..5e4408aebf 100644
--- a/src/southbridge/intel/i82801gx/chip.h
+++ b/src/southbridge/intel/i82801gx/chip.h
@@ -73,6 +73,4 @@ struct southbridge_intel_i82801gx_config {
 	int c4onc3_enable:1;
 };
 
-extern struct chip_operations southbridge_intel_i82801gx_ops;
-
 #endif				/* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */
diff --git a/src/southbridge/intel/pxhd/chip.h b/src/southbridge/intel/pxhd/chip.h
index 5aedb77776..27d88a8277 100644
--- a/src/southbridge/intel/pxhd/chip.h
+++ b/src/southbridge/intel/pxhd/chip.h
@@ -3,4 +3,3 @@ struct southbridge_intel_pxhd_config
 	/* nothing */
 };
 
-extern struct chip_operations southbridge_intel_pxhd_ops;
diff --git a/src/southbridge/intel/sch/chip.h b/src/southbridge/intel/sch/chip.h
index 116d382768..1ae5c32e0c 100644
--- a/src/southbridge/intel/sch/chip.h
+++ b/src/southbridge/intel/sch/chip.h
@@ -35,6 +35,4 @@ struct southbridge_intel_sch_config {
 	uint8_t pirqh_routing;
 };
 
-extern struct chip_operations southbridge_intel_sch_ops;
-
 #endif