summaryrefslogtreecommitdiff
path: root/src/southbridge/intel
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-06-21 13:46:09 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-06-27 17:37:05 +0000
commit9cf2abd6f987d07bf8523473348a6a90d6753590 (patch)
treebb4307884c434a8e1c04f6b5a9dd8b426adb939f /src/southbridge/intel
parentdd7fa543c55239b5d6ca6517dce90974432ddea2 (diff)
sb/intel/i82801jx/fadt.c: Reorder statements
Change the order of the assignments to match that of i82801ix. This changes the binary but the effective result should be the same. Change-Id: Ib190781f26f82f339eaf8039de459376ac0e3a5e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/i82801jx/fadt.c59
1 files changed, 29 insertions, 30 deletions
diff --git a/src/southbridge/intel/i82801jx/fadt.c b/src/southbridge/intel/i82801jx/fadt.c
index c1a753d4ee..29bbe312da 100644
--- a/src/southbridge/intel/i82801jx/fadt.c
+++ b/src/southbridge/intel/i82801jx/fadt.c
@@ -13,6 +13,16 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
struct southbridge_intel_i82801jx_config *chip = dev->chip_info;
u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
+ fadt->sci_int = 0x9;
+
+ if (permanent_smi_handler()) {
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
+ fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
+ fadt->pstate_cnt = APM_CNT_PST_CONTROL;
+ fadt->cst_cnt = APM_CNT_CST_CONTROL;
+ }
+
fadt->pm1a_evt_blk = pmbase;
fadt->pm1b_evt_blk = 0x0;
fadt->pm1a_cnt_blk = pmbase + 0x4;
@@ -29,6 +39,25 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->gpe0_blk_len = 16;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = chip->c3_latency;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1;
+ if (chip->p_cnt_throttling_supported)
+ fadt->duty_width = 3;
+ else
+ fadt->duty_width = 0;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x32;
+ fadt->iapc_boot_arch = 0x03;
+ fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED
+ | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE
+ | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER
+ | ACPI_FADT_C2_MP_SUPPORTED);
+ if (chip->docking_supported)
+ fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
fadt->reset_reg.space_id = 1;
fadt->reset_reg.bit_width = 8;
@@ -93,34 +122,4 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->x_gpe1_blk.access_size = 0;
fadt->x_gpe1_blk.addrl = 0x0;
fadt->x_gpe1_blk.addrh = 0x0;
- fadt->day_alrm = 0xd;
- fadt->mon_alrm = 0x00;
- fadt->century = 0x32;
-
- fadt->sci_int = 0x9;
-
- if (permanent_smi_handler()) {
- fadt->smi_cmd = APM_CNT;
- fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
- fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
- fadt->cst_cnt = APM_CNT_CST_CONTROL;
- fadt->pstate_cnt = APM_CNT_PST_CONTROL;
- }
-
- fadt->p_lvl2_lat = 1;
- fadt->p_lvl3_lat = chip->c3_latency;
- fadt->flush_size = 0;
- fadt->flush_stride = 0;
- fadt->duty_offset = 1;
- if (chip->p_cnt_throttling_supported)
- fadt->duty_width = 3;
- else
- fadt->duty_width = 0;
- fadt->iapc_boot_arch = 0x03;
- fadt->flags = (ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED
- | ACPI_FADT_SLEEP_BUTTON | ACPI_FADT_S4_RTC_WAKE
- | ACPI_FADT_PLATFORM_CLOCK | ACPI_FADT_RESET_REGISTER
- | ACPI_FADT_C2_MP_SUPPORTED);
- if (chip->docking_supported)
- fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED;
}