sb/intel/lynxpoint: Drop unnecessary `UL` suffix

With BUILD_TIMELESS=1, Asrock B85M Pro4 and Google Wolf do not change.

Change-Id: I9ba4097cd82c4ff68315a40e1e955e4ed9a43862
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46719
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 29 insertions, 29 deletions

diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c
index cf360ffc60..68958f08d0 100644
--- a/src/southbridge/intel/lynxpoint/azalia.c
+++ b/src/southbridge/intel/lynxpoint/azalia.c
@@ -33,7 +33,7 @@ static void azalia_pch_init(struct device *dev, u8 *base)
 	u16 reg16;
 	u32 reg32;
 
-	if (RCBA32(0x2030) & (1UL << 31)) {
+	if (RCBA32(0x2030) & (1 << 31)) {
 		reg32 = pci_read_config32(dev, 0x120);
 		reg32 &= 0xf8ffff01;
 		reg32 |= (1 << 25);
@@ -54,9 +54,9 @@ static void azalia_pch_init(struct device *dev, u8 *base)
 	if (pci_read_config32(dev, 0x120) & ((1 << 24) | (1 << 25) | (1 << 26))) {
 		reg32 = pci_read_config32(dev, 0x120);
 		if (pch_is_lp())
-			reg32 &= ~(1UL << 31);
+			reg32 &= ~(1 << 31);
 		else
-			reg32 |= (1UL << 31);
+			reg32 |= (1 << 31);
 		pci_write_config32(dev, 0x120, reg32);
 	}
 
@@ -79,7 +79,7 @@ static void azalia_pch_init(struct device *dev, u8 *base)
 	pci_write_config32(dev, 0xc4, reg32);
 
 	if (!pch_is_lp())
-		pci_and_config32(dev, 0xd0, ~(1UL << 31));
+		pci_and_config32(dev, 0xd0, ~(1 << 31));
 
 	// Select Azalia mode
 	pci_or_config8(dev, 0x40, 1); // Audio Control
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h
index fbad7d020e..d0bfab63bf 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.h
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.h
@@ -40,9 +40,9 @@
 #define GPI_LEVEL		(1 << 30)
 
 #define GPO_LEVEL_SHIFT		31
-#define GPO_LEVEL_MASK		(1UL << GPO_LEVEL_SHIFT)
-#define GPO_LEVEL_LOW		(0UL << GPO_LEVEL_SHIFT)
-#define GPO_LEVEL_HIGH		(1UL << GPO_LEVEL_SHIFT)
+#define GPO_LEVEL_MASK		(1 << GPO_LEVEL_SHIFT)
+#define GPO_LEVEL_LOW		(0 << GPO_LEVEL_SHIFT)
+#define GPO_LEVEL_HIGH		(1 << GPO_LEVEL_SHIFT)
 
 /* conf1 */
 
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 12e262502e..0e6fe640b4 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -338,9 +338,9 @@ static void lpt_lp_pm_init(struct device *dev)
 	pci_or_config32(dev, 0xac, 1 << 21);
 
 	pch_iobp_update(0xED00015C, ~(1 << 11), 0x00003700);
-	pch_iobp_update(0xED000118, ~0UL, 0x00c00000);
-	pch_iobp_update(0xED000120, ~0UL, 0x00240000);
-	pch_iobp_update(0xCA000000, ~0UL, 0x00000009);
+	pch_iobp_update(0xED000118, ~0, 0x00c00000);
+	pch_iobp_update(0xED000120, ~0, 0x00240000);
+	pch_iobp_update(0xCA000000, ~0, 0x00000009);
 
 	/* Set RCBA CIR28 0x3A84 based on SATA port enables */
 	data = 0x00001005;
@@ -392,7 +392,7 @@ static void enable_clock_gating(struct device *dev)
 	u16 reg16;
 
 	/* DMI */
-	RCBA32_AND_OR(0x2234, ~0UL, 0xf);
+	RCBA32_AND_OR(0x2234, ~0, 0xf);
 	reg16 = pci_read_config16(dev, GEN_PMCON_1);
 	reg16 |= (1 << 11) | (1 << 12) | (1 << 14);
 	reg16 |= (1 << 2); // PCI CLKRUN# Enable
@@ -401,7 +401,7 @@ static void enable_clock_gating(struct device *dev)
 
 	reg32 = RCBA32(CG);
 	reg32 |= (1 << 22); // HDA Dynamic
-	reg32 |= (1UL << 31); // LPC Dynamic
+	reg32 |= (1 << 31); // LPC Dynamic
 	reg32 |= (1 << 16); // PCIe Dynamic
 	reg32 |= (1 << 27); // HPET Dynamic
 	reg32 |= (1 << 28); // GPIO Dynamic
@@ -417,7 +417,7 @@ static void enable_lp_clock_gating(struct device *dev)
 	u16 reg16;
 
 	/* DMI */
-	RCBA32_AND_OR(0x2234, ~0UL, 0xf);
+	RCBA32_AND_OR(0x2234, ~0, 0xf);
 	reg16 = pci_read_config16(dev, GEN_PMCON_1);
 	reg16 &= ~((1 << 11) | (1 << 14));
 	reg16 |= (1 << 5) | (1 << 6) | (1 << 7) | (1 << 12) | (1 << 13);
@@ -463,8 +463,8 @@ static void enable_lp_clock_gating(struct device *dev)
 
 	RCBA32_OR(0x38c0, 0x3c07); // SPI Dynamic
 
-	pch_iobp_update(0xCF000000, ~0UL, 0x00007001);
-	pch_iobp_update(0xCE00C000, ~1UL, 0x00000000); // bit0=0 in BWG 1.4.0
+	pch_iobp_update(0xCF000000, ~0, 0x00007001);
+	pch_iobp_update(0xCE00C000, ~1, 0x00000000); // bit0=0 in BWG 1.4.0
 }
 
 static void pch_set_acpi_mode(void)
diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c
index adc011bb7b..1a338b14ec 100644
--- a/src/southbridge/intel/lynxpoint/pch.c
+++ b/src/southbridge/intel/lynxpoint/pch.c
@@ -97,31 +97,31 @@ void pch_disable_devfn(struct device *dev)
 		break;
 	case PCI_DEVFN(21, 0): /* DMA */
 		pch_enable_d3hot(dev);
-		pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS);
+		pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0, SIO_IOBP_FUNCDIS_DIS);
 		break;
 	case PCI_DEVFN(21, 1): /* I2C0 */
 		pch_enable_d3hot(dev);
-		pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS);
+		pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0, SIO_IOBP_FUNCDIS_DIS);
 		break;
 	case PCI_DEVFN(21, 2): /* I2C1 */
 		pch_enable_d3hot(dev);
-		pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS);
+		pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0, SIO_IOBP_FUNCDIS_DIS);
 		break;
 	case PCI_DEVFN(21, 3): /* SPI0 */
 		pch_enable_d3hot(dev);
-		pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS);
+		pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0, SIO_IOBP_FUNCDIS_DIS);
 		break;
 	case PCI_DEVFN(21, 4): /* SPI1 */
 		pch_enable_d3hot(dev);
-		pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS);
+		pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0, SIO_IOBP_FUNCDIS_DIS);
 		break;
 	case PCI_DEVFN(21, 5): /* UART0 */
 		pch_enable_d3hot(dev);
-		pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS);
+		pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0, SIO_IOBP_FUNCDIS_DIS);
 		break;
 	case PCI_DEVFN(21, 6): /* UART1 */
 		pch_enable_d3hot(dev);
-		pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS);
+		pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0, SIO_IOBP_FUNCDIS_DIS);
 		break;
 	case PCI_DEVFN(22, 0): /* MEI #1 */
 		RCBA32_OR(FD2, PCH_DISABLE_MEI1);
@@ -137,7 +137,7 @@ void pch_disable_devfn(struct device *dev)
 		break;
 	case PCI_DEVFN(23, 0): /* SDIO */
 		pch_enable_d3hot(dev);
-		pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS);
+		pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0, SIO_IOBP_FUNCDIS_DIS);
 		break;
 	case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
 		RCBA32_OR(BUC, PCH_DISABLE_GBE);
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 50e0b142af..66cd05e66a 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -167,7 +167,7 @@ void mainboard_config_rcba(void);
 #define GEN_PMCON_2		0xa2
 #define GEN_PMCON_3		0xa4
 #define PMIR			0xac
-#define  PMIR_CF9LOCK		(1UL << 31)
+#define  PMIR_CF9LOCK		(1 << 31)
 #define  PMIR_CF9GR		(1 << 20)
 
 /* GEN_PMCON_3 bits */
@@ -315,7 +315,7 @@ void mainboard_config_rcba(void);
 #define  XHCI_USB3_PORTSC_WRC	(1 << 19)	/* Warm Reset Complete */
 #define  XHCI_USB3_PORTSC_LWS	(1 << 16)	/* Link Write Strobe */
 #define  XHCI_USB3_PORTSC_PED	(1 << 1)	/* Port Enabled/Disabled */
-#define  XHCI_USB3_PORTSC_WPR	(1UL << 31)	/* Warm Port Reset */
+#define  XHCI_USB3_PORTSC_WPR	(1 << 31)	/* Warm Port Reset */
 #define  XHCI_USB3_PORTSC_PLS	(0xf << 5)	/* Port Link State */
 #define   XHCI_PLSR_DISABLED	(4 << 5)	/* Port is disabled */
 #define   XHCI_PLSR_RXDETECT	(5 << 5)	/* Port is disconnected */
@@ -408,7 +408,7 @@ void mainboard_config_rcba(void);
 #define RPFN		0x0404	/* 32bit */
 
 /* Root Port configuratinon space hide */
-#define RPFN_HIDE(port)         (1UL << (((port) * 4) + 3))
+#define RPFN_HIDE(port)         (1 << (((port) * 4) + 3))
 /* Get the function number assigned to a Root Port */
 #define RPFN_FNGET(reg,port)    (((reg) >> ((port) * 4)) & 7)
 /* Set the function number for a Root Port */
diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 308d3c32ce..510440b76a 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -122,7 +122,7 @@ static void sata_init(struct device *dev)
 		reg32 |= 1 << 18;    /* BWG step 10 */
 		reg32 |= 1 << 29;    /* BWG step 11 */
 		if (pch_is_lp()) {
-			reg32 &= ~((1UL << 31) | (1 << 30));
+			reg32 &= ~((1 << 31) | (1 << 30));
 			reg32 |= 1 << 23;
 			reg32 |= 1 << 24; /* Disable listen mode (hotplug) */
 		}
@@ -283,7 +283,7 @@ static void sata_init(struct device *dev)
 
 	reg32 = pci_read_config32(dev, 0x300);
 	reg32 |= (1 << 17) | (1 << 16);
-	reg32 |= (1UL << 31) | (1 << 30) | (1 << 29);
+	reg32 |= (1 << 31) | (1 << 30) | (1 << 29);
 	pci_write_config32(dev, 0x300, reg32);
 }
 
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 9a5e5c0561..8b791f770b 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -348,7 +348,7 @@ static void southbridge_smi_pm1(void)
 	if (pm1_sts & PWRBTN_STS) {
 		/* power button pressed */
 		elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON);
-		disable_pm1_control(-1UL);
+		disable_pm1_control(-1);
 		enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10));
 	}
 }