diff options
| author | Anil Kumar <anil.kumar.k@intel.com> | 2020-05-13 13:07:26 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-05-14 15:36:21 +0000 |
| commit | 7ac6a987d03c3dc9e39c27fda76a2e8642376817 (patch) | |
| tree | 5be735fe77e9b93ca09089cc4ec788a93192993e /src/southbridge/intel | |
| parent | 2412924bc7646fc22b2cb1b9108413fa3e849082 (diff) | |
mb/google/deltaur: Configure GPIO B11 as PMCALERT
GPIO B11 pin should be configured as PMCALERT function. This is
required for the intergrated USB-C feature to work in the SOC
BUG=b:154778458, b:156288164
TEST= build and boot coreboot image on deltan. Test Type-C port
enumeration on Chrome OS
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I8f995901b0a50d2c74f57aba96f86134c9d569e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41378
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel')
0 files changed, 0 insertions, 0 deletions