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authorKyösti Mälkki <kyosti.malkki@gmail.com>2020-12-19 16:19:44 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-18 18:02:27 +0000
commit66c6413c69abb7335efc4ea07f4c811c042704b6 (patch)
tree06d58b85da4c779cca7b78e33a069ea03a4e69e4 /src/southbridge/intel
parentc4a6628a6fe4f5400b7abe1478d0b0b21cb8200f (diff)
ACPI: Refactor ChromeOS specific ACPI GNVS
The layout of GNVS has expectation for a fixed size array for chromeos_acpi_t. This allows us to reduce the exposure of <chromeos/gnvs.h>. If chromeos_acpi_t was the last entry in struct global_nvs padding at the end is also removed. If device_nvs_t exists, place a properly sized reserve for chromeos_acpi_t in the middle. Allocation from cbmem is adjusted such that it matches exactly the OperationRegion size defined inside the ASL. Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/include/soc/nvs.h8
-rw-r--r--src/southbridge/intel/i82801gx/include/soc/nvs.h1
-rw-r--r--src/southbridge/intel/i82801ix/include/soc/nvs.h1
-rw-r--r--src/southbridge/intel/i82801jx/include/soc/nvs.h1
-rw-r--r--src/southbridge/intel/ibexpeak/include/soc/nvs.h1
-rw-r--r--src/southbridge/intel/lynxpoint/include/soc/nvs.h8
6 files changed, 0 insertions, 20 deletions
diff --git a/src/southbridge/intel/bd82x6x/include/soc/nvs.h b/src/southbridge/intel/bd82x6x/include/soc/nvs.h
index 949467b61c..bbfa4c8d21 100644
--- a/src/southbridge/intel/bd82x6x/include/soc/nvs.h
+++ b/src/southbridge/intel/bd82x6x/include/soc/nvs.h
@@ -3,9 +3,7 @@
#ifndef SOUTHBRIDGE_INTEL_BD82X6X_NVS_H
#define SOUTHBRIDGE_INTEL_BD82X6X_NVS_H
-#include <commonlib/helpers.h>
#include <stdint.h>
-#include "vendorcode/google/chromeos/gnvs.h"
struct __packed global_nvs {
/* Miscellaneous */
@@ -103,12 +101,6 @@ struct __packed global_nvs {
u8 tpiq; /* 0xf5 - trackpad IRQ value */
u32 cbmc;
- u8 rsvd13[6]; /* 0xfa - rsvd */
-
- /* ChromeOS specific (starts at 0x100)*/
- chromeos_acpi_t chromeos;
};
-check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-
#endif /* SOUTHBRIDGE_INTEL_BD82X6X_NVS_H */
diff --git a/src/southbridge/intel/i82801gx/include/soc/nvs.h b/src/southbridge/intel/i82801gx/include/soc/nvs.h
index b23b85bec2..cfb44fde7a 100644
--- a/src/southbridge/intel/i82801gx/include/soc/nvs.h
+++ b/src/southbridge/intel/i82801gx/include/soc/nvs.h
@@ -98,7 +98,6 @@ struct __packed global_nvs {
u8 bten;
u32 cbmc;
- u8 rsvd13[10];
};
#endif /* SOUTHBRIDGE_INTEL_I82801GX_NVS_H */
diff --git a/src/southbridge/intel/i82801ix/include/soc/nvs.h b/src/southbridge/intel/i82801ix/include/soc/nvs.h
index 83dd7e508d..e8150dcc86 100644
--- a/src/southbridge/intel/i82801ix/include/soc/nvs.h
+++ b/src/southbridge/intel/i82801ix/include/soc/nvs.h
@@ -98,7 +98,6 @@ struct __packed global_nvs {
u8 bten;
u32 cbmc;
- u8 rsvd13[10];
};
#endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */
diff --git a/src/southbridge/intel/i82801jx/include/soc/nvs.h b/src/southbridge/intel/i82801jx/include/soc/nvs.h
index 96c0a40e05..d2de581aa7 100644
--- a/src/southbridge/intel/i82801jx/include/soc/nvs.h
+++ b/src/southbridge/intel/i82801jx/include/soc/nvs.h
@@ -97,7 +97,6 @@ struct __packed global_nvs {
u8 bten;
u32 cbmc;
- u8 rsvd13[10];
};
#endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */
diff --git a/src/southbridge/intel/ibexpeak/include/soc/nvs.h b/src/southbridge/intel/ibexpeak/include/soc/nvs.h
index bc18c2584d..895591506d 100644
--- a/src/southbridge/intel/ibexpeak/include/soc/nvs.h
+++ b/src/southbridge/intel/ibexpeak/include/soc/nvs.h
@@ -100,7 +100,6 @@ struct __packed global_nvs {
u8 xhci;
u32 cbmc;
- u8 rsvd13[72]; /* rsvd */
};
#endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */
diff --git a/src/southbridge/intel/lynxpoint/include/soc/nvs.h b/src/southbridge/intel/lynxpoint/include/soc/nvs.h
index 154e285a4a..aa35ea05a5 100644
--- a/src/southbridge/intel/lynxpoint/include/soc/nvs.h
+++ b/src/southbridge/intel/lynxpoint/include/soc/nvs.h
@@ -3,9 +3,7 @@
#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H
#define SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H
-#include <commonlib/helpers.h>
#include <stdint.h>
-#include "vendorcode/google/chromeos/gnvs.h"
struct __packed global_nvs {
/* Miscellaneous */
@@ -75,12 +73,6 @@ struct __packed global_nvs {
u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */
u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */
u32 cbmc; /* 0xa0 - 0xa3 - coreboot memconsole */
- u8 rsvd6[92];
-
- /* ChromeOS specific (starts at 0x100)*/
- chromeos_acpi_t chromeos;
};
-check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
-
#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H */