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authorAngel Pons <th3fanbus@gmail.com>2021-01-20 01:22:20 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-02-10 07:29:14 +0000
commitd9e58dca9e72ca2efa62eab832aad606c9c58fcd (patch)
tree565e2a763d0e70c2efcc0ce744599829679a275c /src/southbridge/intel
parenta2a9e607b1e92f322da25d0ca23ce565eb2b17d7 (diff)
nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessors
Drop unused sandybridge.h includes to avoid build failures on Ironlake. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical. Change-Id: If2f0147fe50266e2fe2098cafdf004e51282f5e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/early_rcba.c1
-rw-r--r--src/southbridge/intel/bd82x6x/early_usb.c1
-rw-r--r--src/southbridge/intel/ibexpeak/early_usb.c1
3 files changed, 0 insertions, 3 deletions
diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c
index 29df6a38cb..49c137aec1 100644
--- a/src/southbridge/intel/bd82x6x/early_rcba.c
+++ b/src/southbridge/intel/bd82x6x/early_rcba.c
@@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <northbridge/intel/sandybridge/sandybridge.h>
#include "pch.h"
void southbridge_configure_default_intmap(void)
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
index 8740dcf0c1..654d44b7dc 100644
--- a/src/southbridge/intel/bd82x6x/early_usb.c
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -3,7 +3,6 @@
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/pmbase.h>
diff --git a/src/southbridge/intel/ibexpeak/early_usb.c b/src/southbridge/intel/ibexpeak/early_usb.c
index e76ef7e8a1..bdf711b19d 100644
--- a/src/southbridge/intel/ibexpeak/early_usb.c
+++ b/src/southbridge/intel/ibexpeak/early_usb.c
@@ -3,7 +3,6 @@
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <device/pci_def.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/pmbase.h>