soutbridge/*/bootblock: Use pci_dev_t over device_t typedef

Change-Id: I693b09d588ed6d56177cf86c23497231623b69c0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7193
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>

6 files changed, 9 insertions, 9 deletions

diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index 85a940e2de..b1b53af3ad 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -38,7 +38,7 @@ static void store_initial_timestamp(void)
 static void enable_spi_prefetch(void)
 {
 	u8 reg8;
-	device_t dev;
+	pci_devfn_t dev;
 
 	dev = PCI_DEV(0, 0x1f, 0);
 
@@ -50,7 +50,7 @@ static void enable_spi_prefetch(void)
 
 static void enable_port80_on_lpc(void)
 {
-	device_t dev = PCI_DEV(0, 0x1f, 0);
+	pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
 
 	/* Enable port 80 POST on LPC */
 	pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c
index 7564442946..61ff3018c1 100644
--- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c
+++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c
@@ -43,7 +43,7 @@ static void store_initial_timestamp(void)
 static void enable_spi_prefetch(void)
 {
 	u8 reg8;
-	device_t dev;
+	pci_devfn_t dev;
 
 	dev = PCI_DEV(0, 0x1f, 0);
 
@@ -55,7 +55,7 @@ static void enable_spi_prefetch(void)
 
 static void enable_port80_on_lpc(void)
 {
-	device_t dev = PCI_DEV(0, 0x1f, 0);
+	pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
 
 	/* Enable port 80 POST on LPC */
 	pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c
index b350bde6a9..67afc1ca1a 100644
--- a/src/southbridge/intel/i82371eb/bootblock.c
+++ b/src/southbridge/intel/i82371eb/bootblock.c
@@ -26,7 +26,7 @@
 static void i82371eb_enable_rom(void)
 {
 	u16 reg16;
-	device_t dev;
+	pci_devfn_t dev;
 
 	/*
 	 * Note: The Intel 82371AB/EB/MB ISA device can be on different
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c
index ca0aa92391..7b4cd7d57f 100644
--- a/src/southbridge/intel/i82801gx/bootblock.c
+++ b/src/southbridge/intel/i82801gx/bootblock.c
@@ -34,7 +34,7 @@ static void store_initial_timestamp(void)
 static void enable_spi_prefetch(void)
 {
         u8 reg8;
-        device_t dev;
+        pci_devfn_t dev;
 
         dev = PCI_DEV(0, 0x1f, 0);
 
diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c
index 80b200ea48..fa056a812b 100644
--- a/src/southbridge/intel/i82801ix/bootblock.c
+++ b/src/southbridge/intel/i82801ix/bootblock.c
@@ -22,7 +22,7 @@
 static void enable_spi_prefetch(void)
 {
         u8 reg8;
-        device_t dev;
+        pci_devfn_t dev;
 
         dev = PCI_DEV(0, 0x1f, 0);
 
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 96291189cd..40c6bb8c46 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -38,7 +38,7 @@ static void store_initial_timestamp(void)
 static void enable_spi_prefetch(void)
 {
 	u8 reg8;
-	device_t dev;
+	pci_devfn_t dev;
 
 	dev = PCI_DEV(0, 0x1f, 0);
 
@@ -51,7 +51,7 @@ static void enable_spi_prefetch(void)
 
 static void map_rcba(void)
 {
-	device_t dev = PCI_DEV(0, 0x1f, 0);
+	pci_devfn_t dev = PCI_DEV(0, 0x1f, 0);
 
 	pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
 }