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authorDuncan Laurie <dlaurie@chromium.org>2012-10-10 14:21:23 -0700
committerRonald G. Minnich <rminnich@gmail.com>2012-11-12 17:09:21 +0100
commit23b0053586974e0db70349a272d8cc09167fb4cb (patch)
tree1fa83fb40811ea1b4261d97ed36dbc8fc4428c11 /src/southbridge/intel
parenta571c70c14a86d242be39fc12610b2519499379f (diff)
SPI: Fix and enable Fast Read support
- Fix handling of 5-byte Fast Read command in the ICH SPI driver. This fix is ported from the U-boot driver. - Allow CONFIG_SPI_FLASH_NO_FAST_READ to be overridden by defining a name for the bool in Kconfig and removing the forced select in southbridge config - Fix use of CONFIG_SPI_FLASH_NO_FAST_READ in SPI drivers to use #if instead of #ifdef - Relocate flash functions in SMM so they are usable. This really only needs to happen for read function pointer since it uses a global function rather than a static one from the chip, but it is good to ensure the rest are set up correctly as well. Change-Id: Ic1bb0764cb111f96dd8a389d83b39fe8f5e72fbd Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1775 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel')
-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig1
-rw-r--r--src/southbridge/intel/bd82x6x/spi.c6
2 files changed, 6 insertions, 1 deletions
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 75858c2a67..7634b801ff 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -34,7 +34,6 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
- select SPI_FLASH_NO_FAST_READ
config EHCI_BAR
hex
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index 53b9982192..05649fc85d 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -484,6 +484,12 @@ static void spi_setup_type(spi_transaction *trans)
if (trans->bytesout == 4) { /* and bytesin is > 0 */
trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
}
+
+ /* Fast read command is called with 5 bytes instead of 4 */
+ if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
+ trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
+ --trans->bytesout;
+ }
}
static int spi_setup_opcode(spi_transaction *trans)