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authorPatrick Georgi <patrick@georgi-clan.de>2012-02-16 18:54:37 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-04-12 00:06:11 +0200
commit2c2e78d845cd28eb3b11c87fa3feafaf836cda7a (patch)
tree8eac7f9467d2c13860ae1d23152c9443367b4b85 /src/southbridge/intel/sch
parent5c1ff9284a7ac382a9ec702fa52f3a173279d566 (diff)
Unify IO APIC address specification
Some places still hardcoded the address instead of using IO_APIC_ADDR. Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/677 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/sch')
-rw-r--r--src/southbridge/intel/sch/lpc.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/southbridge/intel/sch/lpc.c b/src/southbridge/intel/sch/lpc.c
index ab180bb713..977e01b4ba 100644
--- a/src/southbridge/intel/sch/lpc.c
+++ b/src/southbridge/intel/sch/lpc.c
@@ -23,6 +23,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <arch/io.h>
+#include <arch/ioapic.h>
#include "chip.h"
/* SCH LPC defines */
@@ -164,8 +165,8 @@ static void sch_lpc_read_resources(device_t dev)
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
- res = new_resource(dev, 3); /* IOAPIC */
- res->base = 0xfec00000;
+ res = new_resource(dev, 3);
+ res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}