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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-06-19 23:05:00 +0300 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-10 01:24:42 +0200 |
| commit | 54d6abd276ac5c60e3846266050167cc1754dcf0 (patch) | |
| tree | decf02bd60f82990b39cae0b93da4e198ab36d63 /src/southbridge/intel/sch | |
| parent | 872c9222965909dffdd091e644b03e676ca2754f (diff) | |
Drop some duplicates of PCI-e config functions
These are not specific to Intel. Further work needs to be done to
combine these with MMCONF_SUPPORT in arch/io.h.
Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3502
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/sch')
| -rw-r--r-- | src/southbridge/intel/sch/smihandler.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c index 2ccbc7f9ba..507413820a 100644 --- a/src/southbridge/intel/sch/smihandler.c +++ b/src/southbridge/intel/sch/smihandler.c @@ -229,13 +229,6 @@ static void dump_tco_status(u32 tco_sts) } #endif - -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -//#include "../../../northbridge/intel/i945/pcie_config.c" - int southbridge_io_trap_handler(int smif) { //global_nvs_t *gnvs = (global_nvs_t *)0xc00; |