diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-11-21 18:42:10 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-12-03 14:17:56 +0100 |
| commit | 21cc96cacd2a2a760524a35298f25dbc59c30072 (patch) | |
| tree | e5c57bc57712b582cf5229d0cfb7cedb557deb7f /src/southbridge/intel/sch/pcie.c | |
| parent | fb509830085e379cee8eb9b5f619c34c249c9d77 (diff) | |
intel/skylake: Remove unused code to add SSDT2
This code is doing nothing and is not needed.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados
Change-Id: I910d443f09a94de1ee0de03cda0577b8847b2de8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ac09fdd7673e5fceb8bfaf1076a8a91e54fc31af
Original-Change-Id: Id989c82853d5a5d5b750def073d34c39816a48d5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313823
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12596
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/sch/pcie.c')
0 files changed, 0 insertions, 0 deletions