intel/sch: Merge northbridge and southbridge in src/soc

Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14599
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

12 files changed, 0 insertions, 1920 deletions

diff --git a/src/southbridge/intel/sch/acpi/ac97.asl b/src/southbridge/intel/sch/acpi/ac97.asl
deleted file mode 100644
index e1db234a63..0000000000
--- a/src/southbridge/intel/sch/acpi/ac97.asl
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Intel i82801G AC'97 Audio and Modem */
-
-// Intel AC'97 Audio 0:1e.2
-
-Device (AUD0)
-{
-	Name (_ADR, 0x001e0002)
-}
-
-// Intel AC'97 Modem 0:1e.3
-
-Device (MODM)
-{
-	Name (_ADR, 0x001e0003)
-
-	Name (_PRW, Package(){ 5, 4 })
-}
diff --git a/src/southbridge/intel/sch/acpi/audio.asl b/src/southbridge/intel/sch/acpi/audio.asl
deleted file mode 100644
index 9e0d997482..0000000000
--- a/src/southbridge/intel/sch/acpi/audio.asl
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Intel i82801G HDA */
-
-// Intel High Definition Audio (Azalia) 0:1b.0
-
-Device (HDEF)
-{
-	Name (_ADR, 0x001b0000)
-
-	// Power Resources for Wake
-	Name (_PRW, Package(){
-		5,  // Bit 5 of GPE
-		4   // Can wake from S4 state.
-	})
-}
diff --git a/src/southbridge/intel/sch/acpi/globalnvs.asl b/src/southbridge/intel/sch/acpi/globalnvs.asl
deleted file mode 100644
index ea53953928..0000000000
--- a/src/southbridge/intel/sch/acpi/globalnvs.asl
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Global Variables */
-
-Name(\PICM, 0)		// IOAPIC/8259
-Name(\DSEN, 1)		// Display Output Switching Enable
-
-/* Global ACPI memory region. This region is used for passing information
- * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
- * Since we don't know where this will end up in memory at ACPI compile time,
- * we have to fix it up in coreboot's ACPI creation phase.
- */
-
-External(NVSA)
-OperationRegion (GNVS, SystemMemory, NVSA, 0x100)
-Field (GNVS, ByteAcc, NoLock, Preserve)
-{
-	/* Miscellaneous */
-	Offset (0x00),
-	OSYS,	16,	// 0x00 - Operating System
-	SMIF,	 8,	// 0x02 - SMI function
-	PRM0,	 8,	// 0x03 - SMI function parameter
-	PRM1,	 8,	// 0x04 - SMI function parameter
-	SCIF,	 8,	// 0x05 - SCI function
-	PRM2,	 8,	// 0x06 - SCI function parameter
-	PRM3,	 8,	// 0x07 - SCI function parameter
-	LCKF,	 8,	// 0x08 - Global Lock function for EC
-	PRM4,	 8,	// 0x09 - Lock function parameter
-	PRM5,	 8,	// 0x0a - Lock function parameter
-	P80D,	32,	// 0x0b - Debug port (IO 0x80) value
-	LIDS,	 8,	// 0x0f - LID state (open = 1)
-	PWRS,	 8,	// 0x10 - Power State (AC = 1)
-	DBGS,	 8,	// 0x11 - Debug State
-	LINX,    8,	// 0x12 - Linux OS
-	DCKN,	 8,	// 0x13 - PCIe docking state
-	/* Thermal policy */
-	Offset (0x14),
-	ACTT,	 8,	// 0x14 - active trip point
-	PSVT,	 8,	// 0x15 - passive trip point
-	TC1V,	 8,	// 0x16 - passive trip point TC1
-	TC2V,	 8,	// 0x17 - passive trip point TC2
-	TSPV,	 8,	// 0x18 - passive trip point TSP
-	CRTT,	 8,	// 0x19 - critical trip point
-	DTSE,	 8,	// 0x1a - Digital Thermal Sensor enable
-	DTS1,	 8,	// 0x1b - DT sensor 1
-	DTS2,	 8,	// 0x1c - DT sensor 2
-	/* Battery Support */
-	Offset (0x1e),
-	BNUM,	 8,	// 0x1e - number of batteries
-	B0SC,	 8,	// 0x1f - BAT0 stored capacity
-	B1SC,	 8,	// 0x20 - BAT1 stored capacity
-	B2SC,	 8,	// 0x21 - BAT2 stored capacity
-	B0SS,	 8,	// 0x22 - BAT0 stored status
-	B1SS,	 8,	// 0x23 - BAT1 stored status
-	B2SS,	 8,	// 0x24 - BAT2 stored status
-	/* Processor Identification */
-	Offset (0x28),
-	APIC,	 8,	// 0x28 - APIC Enabled by coreboot
-	MPEN,	 8,	// 0x29 - Multi Processor Enable
-	PCP0,	 8,	// 0x2a - PDC CPU/CORE 0
-	PCP1,	 8,	// 0x2b - PDC CPU/CORE 1
-	PPCM,	 8,	// 0x2c - Max. PPC state
-	/* Super I/O & CMOS config */
-	Offset (0x32),
-	NATP,	 8,	// 0x32 - ...
-	/* Integrated Graphics Device */
-	Offset (0x3c),
-	IGDS,	 8,	// 0x3c - IGD state (primary = 1)
-	TLST,	 8,	// 0x3d - Display Toggle List pointer
-	CADL,	 8,	// 0x3e - Currently Attached Devices List
-	PADL,	 8,	// 0x3f - Previously Attached Devices List
-	CSTE,	16,	// 0x40 - Current display state
-	NSTE,	16,	// 0x42 - Next display state
-	SSTE,	16,	// 0x44 - Set display state
-	Offset (0x46),
-	NDID,	 8,	// 0x46 - Number of Device IDs
-	DID1,	32,	// 0x47 - Device ID 1
-	DID2,	32,	// 0x4b - Device ID 2
-	DID3,	32,	// 0x4f - Device ID 3
-	DID4,	32,	// 0x53 - Device ID 4
-	DID5,	32,	// 0x57 - Device ID 5
-	/* Backlight Control */
-	Offset (0x64),
-	BLCS,	 8,	// 0x64 - Backlight control possible?
-	BRTL,	 8,	// 0x65 - Brightness Level
-	ODDS,	 8,	// 0x66
-	/* Ambient Light Sensors */
-	Offset (0x6e),
-	ALSE,	 8,	// 0x6e - ALS enable
-	ALAF,	 8,	// 0x6f - Ambient light adjustment factor
-	LLOW,	 8,	// 0x70 - LUX Low
-	LHIH,	 8,	// 0x71 - LUX High
-	/* EMA */
-	Offset (0x78),
-	EMAE,	 8,	// 0x78 - EMA enable
-	EMAP,	16,	// 0x79 - EMA pointer
-	EMAL,	16,	// 0x7b - EMA length
-	/* MEF */
-	Offset (0x82),
-	MEFE,	 8,	// 0x82 - MEF enable
-	/* TPM support */
-	Offset (0x8c),
-	TPMP,	 8,	// 0x8c - TPM
-	TPME,	 8,	// 0x8d - TPM enable
-	/* SATA */
-	Offset (0x96),
-	GTF0,	56,	// 0x96 - GTF task file buffer for port 0
-	GTF1,	56,	// 0x9d - GTF task file buffer for port 1
-	GTF2,	56,	// 0xa4 - GTF task file buffer for port 2
-	IDEM,	 8,	// 0xab - IDE mode (compatible / enhanced)
-	IDET,	 8,	// 0xac - IDE
-	/* IGD OpRegion */
-	Offset (0xb4),
-	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
-	IBTT,	 8,	// 0xb8 - IGD boot panel device
-	IPAT,	 8,	// 0xb9 - IGD panel type cmos option
-	ITVF,	 8,	// 0xba - IGD TV format cmos option
-	ITVM,	 8,	// 0xbb - IGD TV minor format option
-	IPSC,	 8,	// 0xbc - IGD panel scaling
-	IBLC,	 8,	// 0xbd - IGD BLC config
-	IBIA,	 8,	// 0xbe - IGD BIA config
-	ISSC,	 8,	// 0xbf - IGD SSC config
-	I409,	 8,	// 0xc0 - IGD 0409 modified settings
-	I509,	 8,	// 0xc1 - IGD 0509 modified settings
-	I609,	 8,	// 0xc2 - IGD 0609 modified settings
-	I709,	 8,	// 0xc3 - IGD 0709 modified settings
-	IDMM,	 8,	// 0xc4 - IGD DVMT Mode
-	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
-	IF1E,	 8,	// 0xc6 - IGD function 1 enable
-	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
-	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
-	NXD2,	32,	// 0xcc - IGD _DGS next DID2
-	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
-	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
-	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
-	NXD6,	32,	// 0xdc - IGD _DGS next DID6
-	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
-	NXD8,	32,	// 0xe4 - IGD _DGS next DID8
-	/* Mainboard Specific (TODO move elsewhere) */
-	Offset (0xf0),
-	DOCK,	 8,	// 0xf0 - Docking Status
-}
diff --git a/src/southbridge/intel/sch/acpi/irqlinks.asl b/src/southbridge/intel/sch/acpi/irqlinks.asl
deleted file mode 100644
index 2d029242d8..0000000000
--- a/src/southbridge/intel/sch/acpi/irqlinks.asl
+++ /dev/null
@@ -1,487 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Device (LNKA)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 1)
-
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Store (0x80, PRTA)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
-	{
-		IRQ(Level, ActiveLow, Shared)
-			{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
-	})
-
-	// Current Resource Settings for this link
-	Method (_CRS, 0, Serialized)
-	{
-		Name (RTLA, ResourceTemplate()
-		{
-			IRQ(Level, ActiveLow, Shared) {}
-		})
-		CreateWordField(RTLA, 1, IRQ0)
-
-		// Clear the WordField
-		Store (Zero, IRQ0)
-
-		// Set the bit from PRTA
-		ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
-
-		Return (RTLA)
-	}
-
-	// Set Resource Setting for this IRQ link
-	Method (_SRS, 1, Serialized)
-	{
-		CreateWordField(Arg0, 1, IRQ0)
-
-		// Which bit is set?
-		FindSetRightBit(IRQ0, Local0)
-
-		Decrement(Local0)
-		Store(Local0, PRTA)
-	}
-
-	// Status
-	Method (_STA, 0, Serialized)
-	{
-		If(And(PRTA, 0x80)) {
-			Return (0x9)
-		} Else {
-			Return (0xb)
-		}
-	}
-}
-
-Device (LNKB)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 2)
-
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Store (0x80, PRTB)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
-	{
-		IRQ(Level, ActiveLow, Shared)
-			{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
-	})
-
-	// Current Resource Settings for this link
-	Method (_CRS, 0, Serialized)
-	{
-		Name (RTLB, ResourceTemplate()
-		{
-			IRQ(Level, ActiveLow, Shared) {}
-		})
-		CreateWordField(RTLB, 1, IRQ0)
-
-		// Clear the WordField
-		Store (Zero, IRQ0)
-
-		// Set the bit from PRTB
-		ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
-
-		Return (RTLB)
-	}
-
-	// Set Resource Setting for this IRQ link
-	Method (_SRS, 1, Serialized)
-	{
-		CreateWordField(Arg0, 1, IRQ0)
-
-		// Which bit is set?
-		FindSetRightBit(IRQ0, Local0)
-
-		Decrement(Local0)
-		Store(Local0, PRTB)
-	}
-
-	// Status
-	Method (_STA, 0, Serialized)
-	{
-		If(And(PRTB, 0x80)) {
-			Return (0x9)
-		} Else {
-			Return (0xb)
-		}
-	}
-}
-
-Device (LNKC)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 3)
-
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Store (0x80, PRTC)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
-	{
-		IRQ(Level, ActiveLow, Shared)
-			{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
-	})
-
-	// Current Resource Settings for this link
-	Method (_CRS, 0, Serialized)
-	{
-		Name (RTLC, ResourceTemplate()
-		{
-			IRQ(Level, ActiveLow, Shared) {}
-		})
-		CreateWordField(RTLC, 1, IRQ0)
-
-		// Clear the WordField
-		Store (Zero, IRQ0)
-
-		// Set the bit from PRTC
-		ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
-
-		Return (RTLC)
-	}
-
-	// Set Resource Setting for this IRQ link
-	Method (_SRS, 1, Serialized)
-	{
-		CreateWordField(Arg0, 1, IRQ0)
-
-		// Which bit is set?
-		FindSetRightBit(IRQ0, Local0)
-
-		Decrement(Local0)
-		Store(Local0, PRTC)
-	}
-
-	// Status
-	Method (_STA, 0, Serialized)
-	{
-		If(And(PRTC, 0x80)) {
-			Return (0x9)
-		} Else {
-			Return (0xb)
-		}
-	}
-}
-
-Device (LNKD)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 4)
-
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Store (0x80, PRTD)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
-	{
-		IRQ(Level, ActiveLow, Shared)
-			{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
-	})
-
-	// Current Resource Settings for this link
-	Method (_CRS, 0, Serialized)
-	{
-		Name (RTLD, ResourceTemplate()
-		{
-			IRQ(Level, ActiveLow, Shared) {}
-		})
-		CreateWordField(RTLD, 1, IRQ0)
-
-		// Clear the WordField
-		Store (Zero, IRQ0)
-
-		// Set the bit from PRTD
-		ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
-
-		Return (RTLD)
-	}
-
-	// Set Resource Setting for this IRQ link
-	Method (_SRS, 1, Serialized)
-	{
-		CreateWordField(Arg0, 1, IRQ0)
-
-		// Which bit is set?
-		FindSetRightBit(IRQ0, Local0)
-
-		Decrement(Local0)
-		Store(Local0, PRTD)
-	}
-
-	// Status
-	Method (_STA, 0, Serialized)
-	{
-		If(And(PRTD, 0x80)) {
-			Return (0x9)
-		} Else {
-			Return (0xb)
-		}
-	}
-}
-
-Device (LNKE)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 5)
-
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Store (0x80, PRTE)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
-	{
-		IRQ(Level, ActiveLow, Shared)
-			{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
-	})
-
-	// Current Resource Settings for this link
-	Method (_CRS, 0, Serialized)
-	{
-		Name (RTLE, ResourceTemplate()
-		{
-			IRQ(Level, ActiveLow, Shared) {}
-		})
-		CreateWordField(RTLE, 1, IRQ0)
-
-		// Clear the WordField
-		Store (Zero, IRQ0)
-
-		// Set the bit from PRTE
-		ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
-
-		Return (RTLE)
-	}
-
-	// Set Resource Setting for this IRQ link
-	Method (_SRS, 1, Serialized)
-	{
-		CreateWordField(Arg0, 1, IRQ0)
-
-		// Which bit is set?
-		FindSetRightBit(IRQ0, Local0)
-
-		Decrement(Local0)
-		Store(Local0, PRTE)
-	}
-
-	// Status
-	Method (_STA, 0, Serialized)
-	{
-		If(And(PRTE, 0x80)) {
-			Return (0x9)
-		} Else {
-			Return (0xb)
-		}
-	}
-}
-
-Device (LNKF)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 6)
-
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Store (0x80, PRTF)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
-	{
-		IRQ(Level, ActiveLow, Shared)
-			{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
-	})
-
-	// Current Resource Settings for this link
-	Method (_CRS, 0, Serialized)
-	{
-		Name (RTLF, ResourceTemplate()
-		{
-			IRQ(Level, ActiveLow, Shared) {}
-		})
-		CreateWordField(RTLF, 1, IRQ0)
-
-		// Clear the WordField
-		Store (Zero, IRQ0)
-
-		// Set the bit from PRTF
-		ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
-
-		Return (RTLF)
-	}
-
-	// Set Resource Setting for this IRQ link
-	Method (_SRS, 1, Serialized)
-	{
-		CreateWordField(Arg0, 1, IRQ0)
-
-		// Which bit is set?
-		FindSetRightBit(IRQ0, Local0)
-
-		Decrement(Local0)
-		Store(Local0, PRTF)
-	}
-
-	// Status
-	Method (_STA, 0, Serialized)
-	{
-		If(And(PRTF, 0x80)) {
-			Return (0x9)
-		} Else {
-			Return (0xb)
-		}
-	}
-}
-
-Device (LNKG)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 7)
-
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Store (0x80, PRTG)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
-	{
-		IRQ(Level, ActiveLow, Shared)
-			{ 3, 4, 5, 6, 7, 10, 12, 14, 15 }
-	})
-
-	// Current Resource Settings for this link
-	Method (_CRS, 0, Serialized)
-	{
-		Name (RTLG, ResourceTemplate()
-		{
-			IRQ(Level, ActiveLow, Shared) {}
-		})
-		CreateWordField(RTLG, 1, IRQ0)
-
-		// Clear the WordField
-		Store (Zero, IRQ0)
-
-		// Set the bit from PRTG
-		ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
-
-		Return (RTLG)
-	}
-
-	// Set Resource Setting for this IRQ link
-	Method (_SRS, 1, Serialized)
-	{
-		CreateWordField(Arg0, 1, IRQ0)
-
-		// Which bit is set?
-		FindSetRightBit(IRQ0, Local0)
-
-		Decrement(Local0)
-		Store(Local0, PRTG)
-	}
-
-	// Status
-	Method (_STA, 0, Serialized)
-	{
-		If(And(PRTG, 0x80)) {
-			Return (0x9)
-		} Else {
-			Return (0xb)
-		}
-	}
-}
-
-Device (LNKH)
-{
-	Name (_HID, EISAID("PNP0C0F"))
-	Name (_UID, 8)
-
-	// Disable method
-	Method (_DIS, 0, Serialized)
-	{
-		Store (0x80, PRTH)
-	}
-
-	// Possible Resource Settings for this Link
-	Name (_PRS, ResourceTemplate()
-	{
-		IRQ(Level, ActiveLow, Shared)
-			{ 3, 4, 5, 6, 7, 11, 12, 14, 15 }
-	})
-
-	// Current Resource Settings for this link
-	Method (_CRS, 0, Serialized)
-	{
-		Name (RTLH, ResourceTemplate()
-		{
-			IRQ(Level, ActiveLow, Shared) {}
-		})
-		CreateWordField(RTLH, 1, IRQ0)
-
-		// Clear the WordField
-		Store (Zero, IRQ0)
-
-		// Set the bit from PRTH
-		ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
-
-		Return (RTLH)
-	}
-
-	// Set Resource Setting for this IRQ link
-	Method (_SRS, 1, Serialized)
-	{
-		CreateWordField(Arg0, 1, IRQ0)
-
-		// Which bit is set?
-		FindSetRightBit(IRQ0, Local0)
-
-		Decrement(Local0)
-		Store(Local0, PRTH)
-	}
-
-	// Status
-	Method (_STA, 0, Serialized)
-	{
-		If(And(PRTH, 0x80)) {
-			Return (0x9)
-		} Else {
-			Return (0xb)
-		}
-	}
-}
diff --git a/src/southbridge/intel/sch/acpi/lpc.asl b/src/southbridge/intel/sch/acpi/lpc.asl
deleted file mode 100644
index 518bdaef8e..0000000000
--- a/src/southbridge/intel/sch/acpi/lpc.asl
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-// Intel LPC Bus Device  - 0:1f.0
-
-Device (LPCB)
-{
-	Name(_ADR, 0x001f0000)
-
-	OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
-	Field (LPC0, AnyAcc, NoLock, Preserve)
-	{
-		Offset (0x40),
-		PMBS,	16,	// PMBASE
-		Offset (0x60),	// Interrupt Routing Registers
-		PRTA,	8,
-		PRTB,	8,
-		PRTC,	8,
-		PRTD,	8,
-		Offset (0x68),
-		PRTE,	8,
-		PRTF,	8,
-		PRTG,	8,
-		PRTH,	8,
-
-		Offset (0x80),	// IO Decode Ranges
-		IOD0,	8,
-		IOD1,	8,
-
-		Offset (0xf0),	// RCBA
-		RCEN,	1,
-		,	13,
-		RCBA,	18,
-	}
-
-//	#include "irqlinks.asl"
-	#include "irqlinks.asl"
-
-	#include "acpi/ec.asl"
-
-	Device (DMAC)		// DMA Controller
-	{
-		Name(_HID, EISAID("PNP0200"))
-		Name(_CRS, ResourceTemplate()
-		{
-			IO (Decode16, 0x00, 0x00, 0x01, 0x20)
-			IO (Decode16, 0x81, 0x81, 0x01, 0x11)
-			IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
-			IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
-			DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
-		})
-	}
-
-	Device (FWH)		// Firmware Hub
-	{
-		Name (_HID, EISAID("INT0800"))
-		Name (_CRS, ResourceTemplate()
-		{
-			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
-		})
-	}
-
-	Device (HPET)
-	{
-		Name (_HID, EISAID("PNP0103"))
-		Name (_CID, 0x010CD041)
-
-		Name(BUF0, ResourceTemplate()
-		{
-			Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0)
-		})
-
-		Method (_STA, 0)	// Device Status
-		{
-			If (HPTE) {
-				// Note: Ancient versions of Windows don't want
-				// to see the HPET in order to work right
-				If (LGreaterEqual(OSYS, 2001)) {
-					Return (0xf)	// Enable and show device
-				} Else {
-					Return (0xb)	// Enable and don't show device
-				}
-			}
-
-			Return (0x0)	// Not enabled, don't show.
-		}
-
-		Method (_CRS, 0, Serialized) // Current resources
-		{
-			If (HPTE) {
-				CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
-				If (Lequal(HPAS, 1)) {
-					Store(0xfed01000, HPT0)
-				}
-
-				If (Lequal(HPAS, 2)) {
-					Store(0xfed02000, HPT0)
-				}
-
-				If (Lequal(HPAS, 3)) {
-					Store(0xfed03000, HPT0)
-				}
-			}
-
-			Return (BUF0)
-		}
-	}
-
-	Device(PIC)	// 8259 Interrupt Controller
-	{
-		Name(_HID,EISAID("PNP0000"))
-		Name(_CRS, ResourceTemplate()
-		{
-			IO (Decode16, 0x20, 0x20, 0x01, 0x02)
-			IO (Decode16, 0x24, 0x24, 0x01, 0x02)
-			IO (Decode16, 0x28, 0x28, 0x01, 0x02)
-			IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
-			IO (Decode16, 0x30, 0x30, 0x01, 0x02)
-			IO (Decode16, 0x34, 0x34, 0x01, 0x02)
-			IO (Decode16, 0x38, 0x38, 0x01, 0x02)
-			IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
-			IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
-			IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
-			IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
-			IO (Decode16, 0xac, 0xac, 0x01, 0x02)
-			IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
-			IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
-			IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
-			IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
-			IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
-			IRQNoFlags () { 2 }
-		})
-	}
-
-	Device(MATH)	// FPU
-	{
-		Name (_HID, EISAID("PNP0C04"))
-		Name (_CRS, ResourceTemplate()
-		{
-			IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
-			IRQNoFlags() { 13 }
-		})
-	}
-
-	Device(LDRC)	// LPC device: Resource consumption
-	{
-		Name (_HID, EISAID("PNP0C02"))
-		Name (_UID, 2)
-		Name (_CRS, ResourceTemplate()
-		{
-			IO (Decode16, 0x2e, 0x2e, 0x1, 0x02)		// First SuperIO
-			IO (Decode16, 0x4e, 0x4e, 0x1, 0x02)		// Second SuperIO
-			IO (Decode16, 0x61, 0x61, 0x1, 0x01)		// NMI Status
-			IO (Decode16, 0x63, 0x63, 0x1, 0x01)		// CPU Reserved
-			IO (Decode16, 0x65, 0x65, 0x1, 0x01)		// CPU Reserved
-			IO (Decode16, 0x67, 0x67, 0x1, 0x01)		// CPU Reserved
-			IO (Decode16, 0x80, 0x80, 0x1, 0x01)		// Port 80 Post
-			IO (Decode16, 0x92, 0x92, 0x1, 0x01)		// CPU Reserved
-			IO (Decode16, 0xb2, 0xb2, 0x1, 0x02)		// SWSMI
-			// IO (Decode16, 0x680, 0x680, 0x1, 0x70)	// IO ???
-			IO (Decode16, 0x800, 0x800, 0x1, 0x10)		// ACPI I/O trap
-			IO (Decode16, 0x0500, 0x0500, 0x1, 0x80)	// ICH7-M ACPI
-			IO (Decode16, 0x0480, 0x0480, 0x1, 0x40)	// ICH7-M GPIO
-			// IO (Decode16, 0x1640, 0x1640, 0x1, 0x10)	// IO ???
-		})
-	}
-
-	Device (RTC)	// Real Time Clock
-	{
-		Name (_HID, EISAID("PNP0B00"))
-		Name (_CRS, ResourceTemplate()
-		{
-			IO (Decode16, 0x70, 0x70, 1, 8)
-			IRQNoFlags() { 8 }
-		})
-	}
-
-	Device (TIMR)	// Intel 8254 timer
-	{
-		Name(_HID, EISAID("PNP0100"))
-		Name(_CRS, ResourceTemplate()
-		{
-			IO (Decode16, 0x40, 0x40, 0x01, 0x04)
-			IO (Decode16, 0x50, 0x50, 0x10, 0x04)
-			IRQNoFlags() {0}
-		})
-	}
-
-	#include "acpi/superio.asl"
-
-	Device (PS2K)		// Keyboard
-	{
-		Name(_HID, EISAID("PNP0303"))
-		Name(_CID, EISAID("PNP030B"))
-
-		Name(_CRS, ResourceTemplate()
-		{
-			IO (Decode16, 0x60, 0x60, 0x01, 0x01)
-			IO (Decode16, 0x64, 0x64, 0x01, 0x01)
-			IRQ (Edge, ActiveHigh, Exclusive) { 0x01 } // IRQ 1
-		})
-
-		Method (_STA, 0)
-		{
-			Return (0xf)
-		}
-	}
-
-	Device (PS2M)		// Mouse
-	{
-		Name(_HID, EISAID("PNP0F13"))
-		Name(_CRS, ResourceTemplate()
-		{
-			IRQ (Edge, ActiveHigh, Exclusive) { 0x0c } // IRQ 12
-		})
-
-		Method(_STA, 0)
-		{
-			Return (0xf)
-		}
-	}
-
-	Device (FDC0)		// Floppy controller
-	{
-		Name (_HID, EisaId ("PNP0700"))
-		Method (_STA, 0, NotSerialized)
-		{
-			Return (0x0f) // FIXME
-		}
-
-		Name(_CRS, ResourceTemplate()
-		{
-			IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
-			IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
-			IRQNoFlags () {6}
-			DMA (Compatibility, NotBusMaster, Transfer8) {2}
-		})
-
-		Name(_PRS, ResourceTemplate()
-		{
-			IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
-			IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
-			IRQNoFlags () {6}
-			DMA (Compatibility, NotBusMaster, Transfer8) {2}
-		})
-
-	}
-}
diff --git a/src/southbridge/intel/sch/acpi/pata.asl b/src/southbridge/intel/sch/acpi/pata.asl
deleted file mode 100644
index 3d37b672df..0000000000
--- a/src/southbridge/intel/sch/acpi/pata.asl
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-// Intel PATA Controller 0:1f.1
-
-Device (PATA)
-{
-	Name (_ADR, 0x001f0001)
-
-	Device (PRID)
-	{
-		Name (_ADR, 0)
-
-		// Get Timing Mode
-		Method (_GTM)
-		{
-			Name(PBUF, Buffer(20) {
-				0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-				0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-				0x00,0x00,0x00,0x00 })
-
-			CreateDwordField (PBUF,  0, PIO0)
-			CreateDwordField (PBUF,  4, DMA0)
-			CreateDwordField (PBUF,  8, PIO1)
-			CreateDwordField (PBUF, 12, DMA1)
-			CreateDwordField (PBUF, 16, FLAG)
-
-			// TODO fill return structure
-
-			Return (PBUF)
-		}
-
-		// Set Timing Mode
-		Method (_STM, 3)
-		{
-			CreateDwordField (Arg0,  0, PIO0)
-			CreateDwordField (Arg0,  4, DMA0)
-			CreateDwordField (Arg0,  8, PIO1)
-			CreateDwordField (Arg0, 12, DMA1)
-			CreateDwordField (Arg0, 16, FLAG)
-
-			// TODO: Do the deed
-		}
-
-		Device (DSK0)
-		{
-			Name (_ADR, 0)
-			// TODO: _RMV ?
-			// TODO: _GTF ?
-		}
-
-		Device (DSK1)
-		{
-			Name (_ADR, 1)
-
-			// TODO: _RMV ?
-			// TODO: _GTF ?
-		}
-
-	}
-}
diff --git a/src/southbridge/intel/sch/acpi/pci.asl b/src/southbridge/intel/sch/acpi/pci.asl
deleted file mode 100644
index d1b0e8be42..0000000000
--- a/src/southbridge/intel/sch/acpi/pci.asl
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-// Intel PCI to PCI bridge 0:1e.0
-
-Device (PCIB)
-{
-	Name (_ADR, 0x001e0000)
-
-	Device (SLT1)
-	{
-		Name (_ADR, 0x00000000)
-		Name (_PRW, Package(){ 11, 4 })
-	}
-
-	Device (SLT2)
-	{
-		Name (_ADR, 0x00010000)
-		Name (_PRW, Package(){ 11, 4 })
-	}
-
-	Device (SLT3)
-	{
-		Name (_ADR, 0x00020000)
-		Name (_PRW, Package(){ 11, 4 })
-	}
-
-	Device (SLT6)
-	{
-		Name (_ADR, 0x00050000)
-		Name (_PRW, Package(){ 11, 4 })
-	}
-
-	Device (LANC)
-	{
-		Name (_ADR, 0x00080000)
-		Name (_PRW, Package(){ 11, 3 })
-	}
-
-	Device (LANR)
-	{
-		Name (_ADR, 0x00000000)
-		Name (_PRW, Package(){ 11, 3 })
-	}
-
-	// TODO: How many slots, where?
-
-	// PCI Interrupt Routing.
-	// If PICM is set, interrupts are routed over the i8259, otherwise
-	// over the IOAPIC. (Really? If they're above 15 they need to be routed
-	// fixed over the IOAPIC?)
-
-	Method (_PRT)
-	{
-		#include "acpi/southbridge_pci_irqs.asl"
-	}
-
-}
diff --git a/src/southbridge/intel/sch/acpi/pcie.asl b/src/southbridge/intel/sch/acpi/pcie.asl
deleted file mode 100644
index 3c644e2311..0000000000
--- a/src/southbridge/intel/sch/acpi/pcie.asl
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Intel i82801G PCIe support */
-
-// PCI Express Ports
-
-Device (RP01)
-{
-	NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation?
-	//#include "pcie_port.asl"
-	Method(_PRT)
-	{
-		If (PICM) {
-			Return (Package() {
-				Package() { 0x0000ffff, 0, 0, 16 },
-				Package() { 0x0000ffff, 1, 0, 17 },
-				Package() { 0x0000ffff, 2, 0, 18 },
-				Package() { 0x0000ffff, 3, 0, 19 }
-			})
-		} Else {
-			Return (Package() {
-				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
-				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
-				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
-			})
-
-		}
-
-	}
-}
-
-Device (RP02)
-{
-	NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation?
-	//#include "pcie_port.asl"
-	Method(_PRT)
-	{
-		If (PICM) {
-			Return (Package() {
-				Package() { 0x0000ffff, 0, 0, 17 },
-				Package() { 0x0000ffff, 1, 0, 18 },
-				Package() { 0x0000ffff, 2, 0, 19 },
-				Package() { 0x0000ffff, 3, 0, 16 }
-			})
-		} Else {
-			Return (Package() {
-				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
-				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
-				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
-			})
-
-		}
-
-	}
-}
-
-
-Device (RP03)
-{
-	NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation?
-	//#include "pcie_port.asl"
-	Method(_PRT)
-	{
-		If (PICM) {
-			Return (Package() {
-				Package() { 0x0000ffff, 0, 0, 18 },
-				Package() { 0x0000ffff, 1, 0, 19 },
-				Package() { 0x0000ffff, 2, 0, 16 },
-				Package() { 0x0000ffff, 3, 0, 17 }
-			})
-		} Else {
-			Return (Package() {
-				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
-				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
-				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
-				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 }
-			})
-
-		}
-
-	}
-}
-
-
-Device (RP04)
-{
-	NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation?
-	//#include "pcie_port.asl"
-	Method(_PRT)
-	{
-		If (PICM) {
-			Return (Package() {
-				Package() { 0x0000ffff, 0, 0, 19 },
-				Package() { 0x0000ffff, 1, 0, 16 },
-				Package() { 0x0000ffff, 2, 0, 17 },
-				Package() { 0x0000ffff, 3, 0, 18 }
-			})
-		} Else {
-			Return (Package() {
-				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
-				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
-				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
-				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }
-			})
-
-		}
-
-	}
-}
-
-
-Device (RP05)
-{
-	NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation?
-	//#include "pcie_port.asl"
-	Method(_PRT)
-	{
-		If (PICM) {
-			Return (Package() {
-				Package() { 0x0000ffff, 0, 0, 16 },
-				Package() { 0x0000ffff, 1, 0, 17 },
-				Package() { 0x0000ffff, 2, 0, 18 },
-				Package() { 0x0000ffff, 3, 0, 19 }
-			})
-		} Else {
-			Return (Package() {
-				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
-				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
-				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
-			})
-
-		}
-
-	}
-}
-
-
-Device (RP06)
-{
-	NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation?
-	//#include "pcie_port.asl"
-	Method(_PRT)
-	{
-		If (PICM) {
-			Return (Package() {
-				Package() { 0x0000ffff, 0, 0, 17 },
-				Package() { 0x0000ffff, 1, 0, 18 },
-				Package() { 0x0000ffff, 2, 0, 19 },
-				Package() { 0x0000ffff, 3, 0, 16 }
-			})
-		} Else {
-			Return (Package() {
-				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
-				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
-				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
-			})
-
-		}
-
-	}
-}
diff --git a/src/southbridge/intel/sch/acpi/sch.asl b/src/southbridge/intel/sch/acpi/sch.asl
deleted file mode 100644
index c3ee6770d0..0000000000
--- a/src/southbridge/intel/sch/acpi/sch.asl
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Intel i82801G support
- */
-
-Scope(\)
-{
-	// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
-
-	OperationRegion(IO_T, SystemIO, 0x800, 0x10)
-	Field(IO_T, ByteAcc, NoLock, Preserve)
-	{
-		Offset(0x8),
-		TRP0, 8		// IO-Trap at 0x808
-	}
-
-	// ICH7 Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
-	// this doesn't work as ACPI initializes regions and packages first, devices second.
-	// use dynamic operation region? if so, how? XXX
-        //OperationRegion(PMIO, SystemIO, And(\_SB_.PCI0.LPCB.PMBS, 0xfffc), 0x80)
-	OperationRegion(PMIO, SystemIO, 0x500, 0x80)
-	Field(PMIO, ByteAcc, NoLock, Preserve)
-	{
-		Offset(0x42),	// General Purpose Control
-		, 1,		// skip 1 bit
-		GPEC, 1,	// TCO status
-		, 9,		// skip 9 more bits
-		SCIS, 1,	// TCO DMI status
-		, 6		// To the end of the word
-	}
-
-	// ICH7 GPIO IO mapped registers (0x1f.0 reg 0x48.l)
-	OperationRegion(GPIO, SystemIO, 0x1180, 0x3c)
-	Field(GPIO, ByteAcc, NoLock, Preserve)
-	{
-		Offset(0x00),	// GPIO Use Select
-		GU00, 8,
-		GU01, 8,
-		GU02, 8,
-		GU03, 8,
-		Offset(0x04),	// GPIO IO Select
-		GIO0, 8,
-		GIO1, 8,
-		GIO2, 8,
-		GIO3, 8,
-		Offset(0x0c),	// GPIO Level
-		GL00, 8,
-		GL01, 8,
-		, 3,
-		GP27, 1,	// SATA_PWR_EN #0
-		GP28, 1,	// SATA_PWR_EN #1
-		, 3,
-		Offset(0x18),	// GPIO Blink
-		GB00, 8,
-		GB01, 8,
-		GB02, 8,
-		GB03, 8,
-		Offset(0x2c),	// GPIO Invert
-		GIV0, 8,
-		GIV1, 8,
-		GIV2, 8,
-		GIV3, 8,
-		Offset(0x30),	// GPIO Use Select 2
-		GU04, 8,
-		GU05, 8,
-		GU06, 8,
-		GU07, 8,
-		Offset(0x34),	// GPIO IO Select 2
-		GIO4, 8,
-		GIO5, 8,
-		GIO6, 8,
-		GIO7, 8,
-		Offset(0x38),	// GPIO Level 2
-		, 5,
-		GP37, 1,	// PATA_PWR_EN
-		GP38, 1,	// Battery / Power (?)
-		GP39, 1,	// ??
-		GL05, 8,
-		GL06, 8,
-		GL07, 8
-	}
-
-
-	// ICH7 Root Complex Register Block. Memory Mapped through RCBA)
-	OperationRegion(RCRB, SystemMemory, 0xfed1c000, 0x4000)
-	Field(RCRB, DWordAcc, Lock, Preserve)
-	{
-		Offset(0x0000), // Backbone
-		Offset(0x1000), // Chipset
-		Offset(0x3000), // Legacy Configuration Registers
-		Offset(0x3404), // High Performance Timer Configuration
-		HPAS, 2, 	// Address Select
-		, 5,
-		HPTE, 1,	// Address Enable
-		Offset(0x3418), // FD (Function Disable)
-		, 1,		// Reserved
-		PATD, 1,	// PATA disable
-		SATD, 1,	// SATA disable
-		SMBD, 1,	// SMBUS disable
-		HDAD, 1,	// Azalia disable
-		A97D, 1,	// AC'97 disable
-		M97D, 1,	// AC'97 disable
-		ILND, 1,	// Internal LAN disable
-		US1D, 1,	// UHCI #1 disable
-		US2D, 1,	// UHCI #2 disable
-		US3D, 1,	// UHCI #3 disable
-		US4D, 1,	// UHCI #4 disable
-		, 2,		// Reserved
-		LPBD, 1,	// LPC bridge disable
-		EHCD, 1,	// EHCI disable
-		Offset(0x341a), // FD Root Ports
-		RP1D, 1,	// Root Port 1 disable
-		RP2D, 1,	// Root Port 2 disable
-		RP3D, 1,	// Root Port 3 disable
-		RP4D, 1,	// Root Port 4 disable
-		RP5D, 1,	// Root Port 5 disable
-		RP6D, 1		// Root Port 6 disable
-	}
-
-}
-
-// 0:1b.0 High Definition Audio (Azalia)
-#include "audio.asl"
-
-// PCI Express Ports
-#include "pcie.asl"
-
-// USB
-#include "usb.asl"
-
-// PCI Bridge
-#include "pci.asl"
-
-// AC97 Audio and Modem
-#include "ac97.asl"
-
-// LPC Bridge
-#include "lpc.asl"
-
-// PATA
-#include "pata.asl"
-
-// SMBus
-#include "smbus.asl"
diff --git a/src/southbridge/intel/sch/acpi/sleepstates.asl b/src/southbridge/intel/sch/acpi/sleepstates.asl
deleted file mode 100644
index c05835ac3c..0000000000
--- a/src/southbridge/intel/sch/acpi/sleepstates.asl
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(\_S0, Package(4){0x0,0x0,0,0})
-Name(\_S1, Package(4){0x1,0x0,0,0})
-Name(\_S3, Package(4){0x5,0x0,0,0})
-Name(\_S4, Package(4){0x6,0x0,0,0})
-Name(\_S5, Package(4){0x7,0x0,0,0})
diff --git a/src/southbridge/intel/sch/acpi/smbus.asl b/src/southbridge/intel/sch/acpi/smbus.asl
deleted file mode 100644
index 3354b03c4b..0000000000
--- a/src/southbridge/intel/sch/acpi/smbus.asl
+++ /dev/null
@@ -1,240 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-// Intel SMBus Controller 0:1f.3
-
-Device (SBUS)
-{
-	Name (_ADR, 0x001f0003)
-
-	OperationRegion (SMBP, PCI_Config, 0x00, 0x100)
-	Field(SMBP, DWordAcc, NoLock, Preserve)
-	{
-		Offset(0x40),
-		,	2,
-		I2CE,	1
-	}
-
-	/*
-	OperationRegion (SMBI, SystemIO, 0x400, 0x20)
-	Field (SMBI, ByteAcc, NoLock, Preserve)
-	{
-		HSTS,	8,	// Host Status
-		,	8,
-		HCNT,	8,	// Host Control
-		HCMD,	8,	// Host Command
-		TXSA,	8,	// Transmit Slave Address
-		DAT0,	8,	// Host Data 0
-		DAT1,	8,	// Host Data 1
-		HBDB,	8,	// Host Block Data Byte
-		PECK,	8,	// Packet Error Check
-		RXSA,	8,	// Receive Slave Address
-		RXDA,	16,	// Receive Slave Data
-		AUXS,	8,	// Auxiliary Status
-		AUXC,	8,	// Auxiliary Control
-		SLPC,	8,	// SMLink Pin Control
-		SBPC,	8,	// SMBus Pin Control
-		SSTS,	8,	// Slave Status
-		SCMD,	8,	// Slave Command
-		NADR,	8,	// Notify Device Address
-		NDLB,	8,	// Notify Data Low Byte
-		NDLH,	8,	// Notify Data High Byte
-	}
-
-	// Kill all SMBus communication
-	Method (KILL, 0, Serialized)
-	{
-		Or (HCNT, 0x02, HCNT)	// Send Kill
-		Or (HSTS, 0xff, HSTS)	// Clean Status
-	}
-
-	// Check if last operation completed
-	// return	Failure = 0, Success = 1
-	Method (CMPL, 0, Serialized)
-	{
-		Store (4000, Local0)		// Timeout 200ms in 50us steps
-		While (Local0) {
-			If (And(HSTS, 0x02)) {	// Completion Status?
-				Return (1)	// Operation Completed
-			} Else {
-				Stall (50)
-				Decrement (Local0)
-				If (LEqual(Local0, 0)) {
-					KILL()
-				}
-			}
-		}
-
-		Return (0)		//  Failure
-	}
-
-
-	// Wait for SMBus to become ready
-	Method (SRDY, 0, Serialized)
-	{
-		Store (200, Local0)	// Timeout 200ms
-		While (Local0) {
-			If (And(HSTS, 0x40)) {		// IN_USE?
-				Sleep(1)		// Wait 1ms
-				Decrement(Local0)	// timeout--
-				If (LEqual(Local0, 0)) {
-					Return (1)
-				}
-			} Else {
-				Store (0, Local0)	// We're ready
-			}
-		}
-
-		Store (4000, Local0)	// Timeout 200ms (50us * 4000)
-		While (Local0) {
-			If (And (HSTS, 0x01)) {		// Host Busy?
-				Stall(50)		// Wait 50us
-				Decrement(Local0)	// timeout--
-				If (LEqual(Local0, 0)) {
-					KILL()
-				}
-			} Else {
-				Return (0)		// Success
-			}
-		}
-
-		Return (1)		// Failure
-	}
-
-	// SMBus Send Byte
-	// Arg0:	Address
-	// Arg1:	Data
-	// Return:	1 = Success, 0=Failure
-
-	Method (SSXB, 2, Serialized)
-	{
-
-		// Is the SMBus Controller Ready?
-		If (SRDY()) {
-			Return (0)
-		}
-
-		// Send Byte
-		Store (0, I2CE)		// SMBus Enable
-		Store (0xbf, HSTS)
-		Store (Arg0, TXSA)	// Write Address
-		Store (Arg1, HCMD)	// Write Data
-
-		Store (0x48, HCNT)	// Start + Byte Data Protocol
-
-		If (CMPL()) {
-			Or (HSTS, 0xff, HSTS)	// Clean up
-			Return (1)		// Success
-		}
-
-		Return (0)
-	}
-
-
-	// SMBus Receive Byte
-	// Arg0:	Address
-	// Return:	0xffff = Failure, Data (8bit) = Success
-
-	Method (SRXB, 2, Serialized)
-	{
-
-		// Is the SMBus Controller Ready?
-		If (SRDY()) {
-			Return (0xffff)
-		}
-
-		// Receive Byte
-		Store (0, I2CE)		// SMBus Enable
-		Store (0xbf, HSTS)
-		Store (Or (Arg0, 1), TXSA)	// Write Address
-
-		Store (0x44, HCNT)	// Start
-
-		If (CMPL()) {
-			Or (HSTS, 0xff, HSTS)	// Clean up
-			Return (DAT0)		// Success
-		}
-
-		Return (0xffff)
-	}
-
-
-	// SMBus Write Byte
-	// Arg0:	Address
-	// Arg1:	Command
-	// Arg2:	Data
-	// Return:	1 = Success, 0=Failure
-
-	Method (SWRB, 3, Serialized)
-	{
-
-		// Is the SMBus Controller Ready?
-		If (SRDY()) {
-			Return (0)
-		}
-
-		// Send Byte
-		Store (0, I2CE)		// SMBus Enable
-		Store (0xbf, HSTS)
-		Store (Arg0, TXSA)	// Write Address
-		Store (Arg1, HCMD)	// Write Command
-		Store (Arg2, DAT0)	// Write Data
-
-		Store (0x48, HCNT)	// Start + Byte Protocol
-
-		If (CMPL()) {
-			Or (HSTS, 0xff, HSTS)	// Clean up
-			Return (1)		// Success
-		}
-
-		Return (0)
-	}
-
-
-	// SMBus Read Byte
-	// Arg0:	Address
-	// Arg1:	Command
-	// Return:	0xffff = Failure, Data (8bit) = Success
-
-	Method (SRDB, 2, Serialized)
-	{
-
-		// Is the SMBus Controller Ready?
-		If (SRDY()) {
-			Return (0xffff)
-		}
-
-		// Receive Byte
-		Store (0, I2CE)			// SMBus Enable
-		Store (0xbf, HSTS)
-		Store (Or (Arg0, 1), TXSA)	// Write Address
-		Store (Arg1, HCMD)		// Command
-
-		Store (0x48, HCNT)		// Start
-
-		If (CMPL()) {
-			Or (HSTS, 0xff, HSTS)	// Clean up
-			Return (DAT0)		// Success
-		}
-
-		Return (0xffff)
-	}
-	*/
-
-	// Todo: Does anyone ever use these?
-	// Missing: Read / Write Word
-	// Missing: Read / Write Block
-}
diff --git a/src/southbridge/intel/sch/acpi/usb.asl b/src/southbridge/intel/sch/acpi/usb.asl
deleted file mode 100644
index fc5f07c5b2..0000000000
--- a/src/southbridge/intel/sch/acpi/usb.asl
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* Intel i82801G USB support */
-
-// USB Controller 0:1d.0
-
-Device (USB1)
-{
-	Name(_ADR, 0x001d0000)
-
-	OperationRegion(U01P, PCI_Config, 0, 256)
-	Field(U01P, DWordAcc, NoLock, Preserve)
-	{
-		Offset(0xc4),
-		U1WE, 2		// USB Wake Enable
-	}
-
-	Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
-
-	Method (_PSW, 1)	// Power State Wake method
-	{
-		// USB Controller can wake OS from Sleep State
-		If (Arg0) {
-			Store (3, U1WE)
-		} Else {
-			Store (0, U1WE)
-		}
-	}
-
-	// Leave USB ports on for to allow Wake from USB
-
-	Method(_S3D,0)	// Highest D State in S3 State
-	{
-		Return (2)
-	}
-
-	Method(_S4D,0)	// Highest D State in S4 State
-	{
-		Return (2)
-	}
-}
-
-
-// USB Controller 0:1d.1
-
-Device (USB2)
-{
-	Name(_ADR, 0x001d0001)
-
-	OperationRegion(U02P, PCI_Config, 0, 256)
-	Field(U02P, DWordAcc, NoLock, Preserve)
-	{
-		Offset(0xc4),
-		U2WE, 2		// USB Wake Enable
-	}
-
-	Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
-
-	Method (_PSW, 1)	// Power State Wake method
-	{
-		// USB Controller can wake OS from Sleep State
-		If (Arg0) {
-			Store (3, U2WE)
-		} Else {
-			Store (0, U2WE)
-		}
-	}
-
-	// Leave USB ports on for to allow Wake from USB
-
-	Method(_S3D,0)	// Highest D State in S3 State
-	{
-		Return (2)
-	}
-
-	Method(_S4D,0)	// Highest D State in S4 State
-	{
-		Return (2)
-	}
-
-}
-
-
-// USB Controller 0:1d.2
-
-Device (USB3)
-{
-	Name(_ADR, 0x001d0002)
-
-	OperationRegion(U03P, PCI_Config, 0, 256)
-	Field(U03P, DWordAcc, NoLock, Preserve)
-	{
-		Offset(0xc4),
-		U3WE, 2		// USB Wake Enable
-	}
-
-	Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
-
-	Method (_PSW, 1)	// Power State Wake method
-	{
-		// USB Controller can wake OS from Sleep State
-		If (Arg0) {
-			Store (3, U3WE)
-		} Else {
-			Store (0, U3WE)
-		}
-	}
-
-	// Leave USB ports on for to allow Wake from USB
-
-	Method(_S3D,0)	// Highest D State in S3 State
-	{
-		Return (2)
-	}
-
-	Method(_S4D,0)	// Highest D State in S4 State
-	{
-		Return (2)
-	}
-
-}
-
-
-// USB Controller 0:1d.3
-
-Device (USB4)
-{
-	Name(_ADR, 0x001d0003)
-
-	OperationRegion(U04P, PCI_Config, 0, 256)
-	Field(U04P, DWordAcc, NoLock, Preserve)
-	{
-		Offset(0xc4),
-		U4WE, 2		// USB Wake Enable
-	}
-
-	Name (_PRW, Package(){ 3, 4 }) // Power Resources for Wake
-
-	Method (_PSW, 1)	// Power State Wake method
-	{
-		// USB Controller can wake OS from Sleep State
-		If (Arg0) {
-			Store (3, U4WE)
-		} Else {
-			Store (0, U4WE)
-		}
-	}
-
-	// Leave USB ports on for to allow Wake from USB
-
-	Method(_S3D,0)	// Highest D State in S3 State
-	{
-		Return (2)
-	}
-
-	Method(_S4D,0)	// Highest D State in S4 State
-	{
-		Return (2)
-	}
-
-}
-
-
-// EHCI Controller 0:1d.7
-
-Device (EHC1)
-{
-	Name(_ADR, 0x001d0007)
-
-	Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
-
-	// Leave USB ports on for to allow Wake from USB
-
-	Method(_S3D,0)	// Highest D State in S3 State
-	{
-		Return (2)
-	}
-
-	Method(_S4D,0)	// Highest D State in S4 State
-	{
-		Return (2)
-	}
-
-	Device (HUB7)
-	{
-		Name (_ADR, 0x00000000)
-
-		// How many are there?
-		Device (PRT1) { Name (_ADR, 1) } // USB Port 0
-		Device (PRT2) { Name (_ADR, 2) } // USB Port 1
-		Device (PRT3) { Name (_ADR, 3) } // USB Port 2
-		Device (PRT4) { Name (_ADR, 4) } // USB Port 3
-		Device (PRT5) { Name (_ADR, 5) } // USB Port 4
-		Device (PRT6) { Name (_ADR, 6) } // USB Port 5
-	}
-}