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| author | Rudolf Marek <r.marek@assembler.cz> | 2008-12-04 23:37:12 +0000 |
|---|---|---|
| committer | Rudolf Marek <r.marek@assembler.cz> | 2008-12-04 23:37:12 +0000 |
| commit | 31e52e61aa4cbe3065ea86732a689ab4cf58984f (patch) | |
| tree | b7832dc8aa31f7ec64a6742b6be1f2017c9d935f /src/southbridge/intel/pxhd | |
| parent | 1162f25a49e8f39822123d664cda10fef466b351 (diff) | |
The patch changes the LDTSTOP length as well mostly default content of 0xec,
0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong.
Furthermore this fix for powernow may not work on CPUs hit by errata #181.
Workaround should be implemented. The powernow may not work on pre-A2 revisions
of VT8237S silicon, revision reg is unknown.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/pxhd')
0 files changed, 0 insertions, 0 deletions