summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/lynxpoint
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2021-12-28 13:05:56 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-01-04 11:48:19 +0000
commitaf4bd5633debc8838b563c3fadd96e2b4b060ab5 (patch)
tree6867d466f6e3b7ca8e6077979a404caf7609a747 /src/southbridge/intel/lynxpoint
parent0b9d186e3dc7c209d0fc26b61db3cd98550b71bd (diff)
sb/intel: Use `bool` for PCIe coalescing option
Retype the `pcie_port_coalesce` devicetree options and related variables to better reflect their bivalue (boolean) nature. Change-Id: I6a4dfe277a8f83a9eb58515fc4eaa2fee0747ddb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60416 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
-rw-r--r--src/southbridge/intel/lynxpoint/chip.h2
-rw-r--r--src/southbridge/intel/lynxpoint/pcie.c4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h
index 89bbb1ce0c..12bb401f77 100644
--- a/src/southbridge/intel/lynxpoint/chip.h
+++ b/src/southbridge/intel/lynxpoint/chip.h
@@ -65,7 +65,7 @@ struct southbridge_intel_lynxpoint_config {
uint32_t gen4_dec;
/* Enable linear PCIe Root Port function numbers starting at zero */
- uint8_t pcie_port_coalesce;
+ bool pcie_port_coalesce;
/* Force root port ASPM configuration with port bitmap */
uint8_t pcie_port_force_aspm;
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 5f21e619a5..30773e63b2 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -28,7 +28,7 @@ struct root_port_config {
u32 b0d28f0_32c;
u32 b0d28f4_32c;
u32 b0d28f5_32c;
- int coalesce;
+ bool coalesce;
int gbe_port;
int num_ports;
struct device *ports[MAX_NUM_ROOT_PORTS];
@@ -304,7 +304,7 @@ static void root_port_commit_config(void)
/* If the first root port is disabled the coalesce ports. */
if (!is_rp_enabled(1))
- rpc.coalesce = 1;
+ rpc.coalesce = true;
/* Perform clock gating configuration. */
pcie_enable_clock_gating();