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authorStefan Reinauer <reinauer@chromium.org>2013-03-21 11:51:41 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-22 00:00:09 +0100
commit24d1d4b47274eb82893e6726472a991a36fce0aa (patch)
tree57126316330f6f9d407f605fa831ce530650f069 /src/southbridge/intel/lynxpoint
parent55ed3106556a9bcbe36d3389dc5230d4a4ee2a40 (diff)
x86: Unify arch/io.h and arch/romcc_io.h
Here's the great news: From now on you don't have to worry about hitting the right io.h include anymore. Just forget about romcc_io.h and use io.h instead. This cleanup has a number of advantages, like you don't have to guard device/ includes for SMM and pre RAM anymore. This allows to get rid of a number of ifdefs and will generally make the code more readable and understandable. Potentially in the future some of the code in the io.h __PRE_RAM__ path should move to device.h or other device/ includes instead, but that's another incremental change. Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2872 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
-rw-r--r--src/southbridge/intel/lynxpoint/bootblock.c1
-rw-r--r--src/southbridge/intel/lynxpoint/early_me.c1
-rw-r--r--src/southbridge/intel/lynxpoint/early_pch.c1
-rw-r--r--src/southbridge/intel/lynxpoint/early_smbus.c1
-rw-r--r--src/southbridge/intel/lynxpoint/early_spi.c1
-rw-r--r--src/southbridge/intel/lynxpoint/early_usb.c1
-rw-r--r--src/southbridge/intel/lynxpoint/finalize.c1
-rw-r--r--src/southbridge/intel/lynxpoint/gpio.c6
-rw-r--r--src/southbridge/intel/lynxpoint/lp_gpio.c4
-rw-r--r--src/southbridge/intel/lynxpoint/me_9.x.c9
-rw-r--r--src/southbridge/intel/lynxpoint/smihandler.c1
-rw-r--r--src/southbridge/intel/lynxpoint/spi.c1
-rw-r--r--src/southbridge/intel/lynxpoint/usb_debug.c1
13 files changed, 2 insertions, 27 deletions
diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c
index 2770d55cad..96291189cd 100644
--- a/src/southbridge/intel/lynxpoint/bootblock.c
+++ b/src/southbridge/intel/lynxpoint/bootblock.c
@@ -18,7 +18,6 @@
*/
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <cpu/x86/tsc.h>
#include "pch.h"
diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c
index e41b801a8b..6b61eac3db 100644
--- a/src/southbridge/intel/lynxpoint/early_me.c
+++ b/src/southbridge/intel/lynxpoint/early_me.c
@@ -21,7 +21,6 @@
#include <arch/hlt.h>
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <console/console.h>
#include <delay.h>
#include <device/pci_ids.h>
diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c
index 3709aed63b..a390d737bc 100644
--- a/src/southbridge/intel/lynxpoint/early_pch.c
+++ b/src/southbridge/intel/lynxpoint/early_pch.c
@@ -20,7 +20,6 @@
#include <console/console.h>
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <device/pci_def.h>
#include <elog.h>
#include "pch.h"
diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c
index a626649e2b..9de97e7fe2 100644
--- a/src/southbridge/intel/lynxpoint/early_smbus.c
+++ b/src/southbridge/intel/lynxpoint/early_smbus.c
@@ -19,7 +19,6 @@
*/
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <console/console.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/lynxpoint/early_spi.c b/src/southbridge/intel/lynxpoint/early_spi.c
index ddfc4c2261..6f57f637a9 100644
--- a/src/southbridge/intel/lynxpoint/early_spi.c
+++ b/src/southbridge/intel/lynxpoint/early_spi.c
@@ -19,7 +19,6 @@
*/
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <console/console.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c
index b2e009123e..ebd5c2c50a 100644
--- a/src/southbridge/intel/lynxpoint/early_usb.c
+++ b/src/southbridge/intel/lynxpoint/early_usb.c
@@ -19,7 +19,6 @@
*/
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <console/console.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c
index 2cece13e17..d9bc22531c 100644
--- a/src/southbridge/intel/lynxpoint/finalize.c
+++ b/src/southbridge/intel/lynxpoint/finalize.c
@@ -19,7 +19,6 @@
*/
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <console/post_codes.h>
#include <spi-generic.h>
#include "pch.h"
diff --git a/src/southbridge/intel/lynxpoint/gpio.c b/src/southbridge/intel/lynxpoint/gpio.c
index 9d36887dd1..b492068ccd 100644
--- a/src/southbridge/intel/lynxpoint/gpio.c
+++ b/src/southbridge/intel/lynxpoint/gpio.c
@@ -20,14 +20,8 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
-
-#ifdef __PRE_RAM__
-#include <arch/romcc_io.h>
-#else
#include <device/device.h>
#include <device/pci.h>
-#endif
-
#include "pch.h"
#include "gpio.h"
diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c
index 2d2e0576ea..a6e4f5c998 100644
--- a/src/southbridge/intel/lynxpoint/lp_gpio.c
+++ b/src/southbridge/intel/lynxpoint/lp_gpio.c
@@ -20,12 +20,8 @@
#include <stdint.h>
#include <string.h>
#include <arch/io.h>
-#ifdef __PRE_RAM__
-#include <arch/romcc_io.h>
-#else
#include <device/device.h>
#include <device/pci.h>
-#endif
#include "pch.h"
#include "lp_gpio.h"
diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 2e790fc2a5..a16879b757 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -31,19 +31,14 @@
#include <arch/hlt.h>
#include <arch/io.h>
#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_def.h>
#include <string.h>
#include <delay.h>
#include <elog.h>
-#ifdef __SMM__
-# include <arch/romcc_io.h>
-#else
-# include <device/device.h>
-# include <device/pci.h>
-#endif
-
#include "me.h"
#include "pch.h"
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 49f7df8d52..203a1bbfb5 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -23,7 +23,6 @@
#include <types.h>
#include <arch/hlt.h>
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <device/pci_def.h>
diff --git a/src/southbridge/intel/lynxpoint/spi.c b/src/southbridge/intel/lynxpoint/spi.c
index 123c6a9d62..eaa17d5e21 100644
--- a/src/southbridge/intel/lynxpoint/spi.c
+++ b/src/southbridge/intel/lynxpoint/spi.c
@@ -34,7 +34,6 @@
#define min(a, b) ((a)<(b)?(a):(b))
#ifdef __SMM__
-#include <arch/romcc_io.h>
#define pci_read_config_byte(dev, reg, targ)\
*(targ) = pci_read_config8(dev, reg)
#define pci_read_config_word(dev, reg, targ)\
diff --git a/src/southbridge/intel/lynxpoint/usb_debug.c b/src/southbridge/intel/lynxpoint/usb_debug.c
index 1cee353e2d..d8da7b5484 100644
--- a/src/southbridge/intel/lynxpoint/usb_debug.c
+++ b/src/southbridge/intel/lynxpoint/usb_debug.c
@@ -19,7 +19,6 @@
#include <stdint.h>
#include <arch/io.h>
-#include <arch/romcc_io.h>
#include <console/console.h>
#include <usbdebug.h>
#include <device/pci_def.h>