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authorDuncan Laurie <dlaurie@chromium.org>2012-12-17 11:11:26 -0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-14 18:24:14 +0100
commitfb9928f2ec240babb5d3138136c03a7a78c53cc4 (patch)
treeac848cb77290b7ae08cd4fd743326033c56a2551 /src/southbridge/intel/lynxpoint
parentbe98524ab208be4764c7d79bdcc7c35162210af1 (diff)
lynxpoint: Add Kconfig entry for Low Power chipset
There are enough subtle differences that it is useful to have a Kconfig entry to differentiate the ULT/LP chipet from the desktop/mobile versions. Change-Id: I04ca1bc6f90bcf9e6994ea7125c98347e8def898 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2645 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
-rw-r--r--src/southbridge/intel/lynxpoint/Kconfig6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index e1d0e3591d..6f5bfe2313 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -32,6 +32,12 @@ config SOUTH_BRIDGE_OPTIONS # dummy
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
+config INTEL_LYNXPOINT_LP
+ bool
+ default n
+ help
+ Set this option to y for Lynxpont LP (Haswell ULT).
+
config EHCI_BAR
hex
default 0xfef00000