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authorAngel Pons <th3fanbus@gmail.com>2021-01-28 14:27:46 +0100
committerPatrick Georgi <pgeorgi@google.com>2021-02-06 09:08:15 +0000
commitb70ff52b83d5ffe9feca95d086a5366dd6f6ce4d (patch)
treecb78016240a6c4cd35905230d7f0f807eedbe91e /src/southbridge/intel/lynxpoint
parentca935d1107ccc3ba77cc6915360f17f38e2f328d (diff)
intel: Define `RCBA_LENGTH` in Kconfig and use it
Change-Id: Ief81d49f04c1743b2a37633c4a35da9d6ddb0974 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50039 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
-rw-r--r--src/southbridge/intel/lynxpoint/acpi/pch.asl2
-rw-r--r--src/southbridge/intel/lynxpoint/lpc.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl
index f97a5ad58d..50f73cdf9c 100644
--- a/src/southbridge/intel/lynxpoint/acpi/pch.asl
+++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl
@@ -19,7 +19,7 @@ Scope (\)
}
// Root Complex Register Block
- OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, 0x4000)
+ OperationRegion (RCRB, SystemMemory, CONFIG_FIXED_RCBA_MMIO_BASE, CONFIG_RCBA_LENGTH)
Field (RCRB, DWordAcc, Lock, Preserve)
{
Offset (0x3404), // High Performance Timer Configuration
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 20b9b4318f..b0ff5450cf 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -560,7 +560,7 @@ static void pch_lpc_add_mmio_resources(struct device *dev)
if (CONFIG_FIXED_RCBA_MMIO_BASE < default_decode_base) {
res = new_resource(dev, RCBA);
res->base = (resource_t)CONFIG_FIXED_RCBA_MMIO_BASE;
- res->size = 16 * 1024;
+ res->size = CONFIG_RCBA_LENGTH;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
IORESOURCE_FIXED | IORESOURCE_RESERVE;
}