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authorAngel Pons <th3fanbus@gmail.com>2021-03-01 22:57:21 +0100
committerAngel Pons <th3fanbus@gmail.com>2021-03-10 10:59:36 +0000
commit34be1be2403514741495c95c01a21de4cd6e014a (patch)
tree795ec5cae752bf0478c00a24233a36e280dc6c4c /src/southbridge/intel/lynxpoint
parentae999503f62ef8a3b9b2756a2810d29c383a009e (diff)
nb/intel/haswell: Finalize northbridge in ramstage
There's no need to finalize the northbridge in SMM. This also makes unification with Broadwell easier. Tested on Asrock B85M Pro4, still boots and registers get locked. Change-Id: I8b2c0d14a79e4fcd2e8985ce58542791cef9b1fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
-rw-r--r--src/southbridge/intel/lynxpoint/smihandler.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 7f81dd20d6..c2f34ab242 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -273,7 +273,6 @@ static void southbridge_smi_apmc(void)
}
intel_pch_finalize_smm();
- intel_northbridge_haswell_finalize_smm();
intel_cpu_haswell_finalize_smm();
chipset_finalized = 1;