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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-14 05:41:41 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-15 06:55:59 +0000
commitfaf20d30a6e451d45e29613e3f4603dc72771843 (patch)
treed1c3df6e87473d66633fb3a4a8cec736fdda2cd7 /src/southbridge/intel/lynxpoint
parentf091f4daf7e76cff3cdf9b7a19bb77281fb6af9d (diff)
soc/intel: Rename some SMM support functions
Rename southbridge_smm_X to smm_southbridge_X. Rename most southcluster_smm_X to smm_southbridge_X. Change-Id: I4f6f9207ba32cf51d75b9ca9230e38310a33a311 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34856 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/lynxpoint')
-rw-r--r--src/southbridge/intel/lynxpoint/pch.h8
-rw-r--r--src/southbridge/intel/lynxpoint/smi.c9
2 files changed, 5 insertions, 12 deletions
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 626d22d57f..540a4d3574 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -183,14 +183,6 @@ void pch_log_state(void);
void acpi_create_intel_hpet(acpi_hpet_t * hpet);
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
-/* These helpers are for performing SMM relocation. */
-void southbridge_trigger_smi(void);
-void southbridge_clear_smi_status(void);
-/* The initialization of the southbridge is split into 2 compoments. One is
- * for clearing the state in the SMM registers. The other is for enabling
- * SMIs. They are split so that other work between the 2 actions. */
-void southbridge_smm_clear_state(void);
-void southbridge_smm_enable_smi(void);
#else
void enable_smbus(void);
void enable_usb_bar(void);
diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c
index 3a6c4038c8..4fb00b507a 100644
--- a/src/southbridge/intel/lynxpoint/smi.c
+++ b/src/southbridge/intel/lynxpoint/smi.c
@@ -19,12 +19,13 @@
#include <device/pci.h>
#include <console/console.h>
#include <arch/io.h>
+#include <cpu/intel/smm_reloc.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/smm.h>
#include "pch.h"
-void southbridge_smm_clear_state(void)
+void smm_southbridge_clear_state(void)
{
u32 smi_en;
@@ -50,7 +51,7 @@ void southbridge_smm_clear_state(void)
clear_gpe_status();
}
-void southbridge_smm_enable_smi(void)
+void smm_southbridge_enable_smi(void)
{
printk(BIOS_DEBUG, "Enabling SMIs.\n");
/* Configure events */
@@ -68,7 +69,7 @@ void southbridge_smm_enable_smi(void)
enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS);
}
-void southbridge_trigger_smi(void)
+static void __unused southbridge_trigger_smi(void)
{
/**
* There are several methods of raising a controlled SMI# via
@@ -88,7 +89,7 @@ void southbridge_trigger_smi(void)
outb(0x00, 0xb2);
}
-void southbridge_clear_smi_status(void)
+static void __unused southbridge_clear_smi_status(void)
{
/* Clear SMI status */
clear_smi_status();